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<title>CMSIS-Core (Cortex-M): Revision History of CMSIS-Core (Cortex-M)</title>
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   <div id="projectname">CMSIS-Core (Cortex-M)
   &#160;<span id="projectnumber">Version 5.3.0</span>
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   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<div class="title">Revision History of CMSIS-Core (Cortex-M) </div>  </div>
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<div class="contents">
<div class="textblock"><dl class="todo"><dt><b><a class="el" href="todo.html#_todo000001">Todo:</a></b></dt><dd>complete History for V5.x.x</dd></dl>
<table class="cmtable" summary="Revision History">
<tr>
<th>Version </th><th>Description  </th></tr>
<tr>
<td>V5.x.x </td><td>Modified: TrustZone setup with <a class="el" href="partition_h_pg.html">TrustZone setup: partition_&lt;device&gt;.h</a> and <a class="el" href="partition_h_pg.html#partition_gen_h_pg">Region/ISR setup: partition_gen.h</a>.   </td></tr>
<tr>
<td>V5.3.0 </td><td>Added: Provisions for compiler-independent C startup code.   </td></tr>
<tr>
<td>V5.2.1 </td><td>Fixed: Compilation issue in cmsis_armclang_ltm.h introduced in 5.2.0   </td></tr>
<tr>
<td>V5.2.0 </td><td>Added: Cortex-M35P support.<br  />
 Added: Cortex-M1 support.<br  />
 Added: Armv8.1 architecture support.<br  />
 Added: <a class="el" href="group__compiler__conntrol__gr.html#ga378ac21329d33f561f90265eef89f564">__RESTRICT</a> and <a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> compiler control macros.   </td></tr>
<tr>
<td>V5.1.2 </td><td>Removed using get/set built-ins FPSCR in GCC &gt;= 7.2 due to shortcomings.<br  />
 Added __NO_RETURN to __NVIC_SystemReset() to silence compiler warnings.<br  />
 Added support for Cortex-M1 (beta). <br  />
 Removed usage of register keyword. <br  />
 Added defines for EXC_RETURN, FNC_RETURN and integrity signature values. <br  />
 Enhanced MPUv7 API with defines for memory access attributes.   </td></tr>
<tr>
<td>V5.1.1 </td><td>Aligned MSPLIM and PSPLIM access functions along supported compilers.   </td></tr>
<tr>
<td>V5.1.0 </td><td>Added MPU Functions for ARMv8-M for Cortex-M23/M33.<br  />
 Moved __SSAT and __USAT intrinsics to CMSIS-Core.<br  />
 Aligned __REV, __REV16 and __REVSH intrinsics along supported compilers.   </td></tr>
<tr>
<td>V5.0.2 </td><td>Added macros <a class="el" href="group__compiler__conntrol__gr.html#gabe8693a7200e573101551d49a1772fb9">__UNALIGNED_UINT16_READ</a>, __UNALIGNED_UINT16_WRITE.<br  />
 Added macros <a class="el" href="group__compiler__conntrol__gr.html#ga254322c344d954c9f829719a50a88e87">__UNALIGNED_UINT32_READ</a>, __UNALIGNED_UINT32_WRITE.<br  />
 Deprecated macro __UNALIGNED_UINT32.<br  />
 Changed <a class="el" href="group__version__control__gr.html">Version Control</a> macros to be core agnostic. <br  />
 Added <a class="el" href="group__mpu__functions.html">MPU Functions for Armv6-M/v7-M</a> for Cortex-M0+/M3/M4/M7.   </td></tr>
<tr>
<td>V5.0.1 </td><td>Added: macro <a class="el" href="group__compiler__conntrol__gr.html#ga4dbb70fab85207c27b581ecb6532b314">__PACKED_STRUCT</a>. <br  />
 Added: uVisor support. <br  />
   </td></tr>
<tr>
<td>V5.00 </td><td>Added: Cortex-M23, Cortex-M33 support.<br  />
 Added: macro __SAU_PRESENT with __SAU_REGION_PRESENT. <br  />
 Replaced: macro __SAU_PRESENT with __SAU_REGION_PRESENT. <br  />
 Reworked: SAU register and functions. <br  />
 Added: macro <a class="el" href="group__compiler__conntrol__gr.html#ga0c58caa5a273e2c21924509a45f8b849">__ALIGNED</a>. <br  />
 Updated: function <a class="el" href="group__Icache__functions__m7.html#gaf9e7c6c8e16ada1f95e5bf5a03505b68">SCB_EnableICache</a>. <br  />
 Added: cmsis_compiler.h with compiler specific CMSIS macros, functions, instructions. <br  />
 Added: macro <a class="el" href="group__compiler__conntrol__gr.html#gabe8996d3d985ee1529475443cc635bf1">__PACKED</a>. <br  />
 Updated: compiler specific include files. <br  />
 Updated: core dependant include files. <br  />
 Removed: deprecated files core_cmfunc.h, core_cminstr.h, core_cmsimd.h.   </td></tr>
<tr>
<td>V5.00<br  />
Beta 6 </td><td>Added: SCB_CFSR register bit definitions. <br  />
 Added: function <a class="el" href="group__NVIC__gr.html#ga72f102d31af0ee4aa7a6fb7a180840f3">NVIC_GetEnableIRQ</a>. <br  />
 Updated: core instruction macros <a class="el" href="group__intrinsic__CPU__gr.html#gac71fad9f0a91980fecafcb450ee0a63e">__NOP</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gaed91dfbf3d7d7b7fba8d912fcbeaad88">__WFI</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gad3efec76c3bfa2b8528ded530386c563">__WFE</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga3c34da7eb16496ae2668a5b95fa441e7">__SEV</a> for toolchain GCC.   </td></tr>
<tr>
<td>V5.00<br  />
Beta 5 </td><td>Moved: DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib. <br  />
 Added: DSP libraries build projects to CMSIS pack.   </td></tr>
<tr>
<td>V5.00<br  />
Beta 4 </td><td>Updated: ARMv8M device files. <br  />
 Corrected: ARMv8MBL interrupts. <br  />
 Reworked: NVIC functions.   </td></tr>
<tr>
<td>V5.00<br  />
Beta 2 </td><td>Changed: ARMv8M SAU regions to 8. <br  />
 Changed: moved function <a class="el" href="group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1">TZ_SAU_Setup</a> to file partition_&lt;device&gt;.h. <br  />
 Changed: license under Apache-2.0. <br  />
 Added: check if macro is defined before use. <br  />
 Corrected: function <a class="el" href="group__Dcache__functions__m7.html#ga6468170f90d270caab8116e7a4f0b5fe">SCB_DisableDCache</a>. <br  />
 Corrected: macros <a class="el" href="Ref__Peripheral_8txt.html#a286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>, <a class="el" href="Ref__Peripheral_8txt.html#a139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>. <br  />
 Added: NVIC function virtualization with macros <a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a> and <a class="el" href="group__NVIC__gr.html#gad01d3aa220b50ef141b06c93888b268d">CMSIS_VECTAB_VIRTUAL</a>.   </td></tr>
<tr>
<td>V5.00<br  />
Beta 1 </td><td>Renamed: cmsis_armcc_V6.h to cmsis_armclang.h.<br  />
 Renamed: core_*.h to lower case.<br  />
 Added: function <a class="el" href="group__fpu__functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756">SCB_GetFPUType</a> to all CMSIS cores.<br  />
 Added: ARMv8-M support.  &lt;/tr </td></tr>
<tr>
<td>V4.30 </td><td>Corrected: DoxyGen function parameter comments.<br  />
 Corrected: IAR toolchain: removed for <a class="el" href="group__NVIC__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46">NVIC_SystemReset</a> the attribute(noreturn).<br  />
 Corrected: GCC toolchain: suppressed irrelevant compiler warnings.<br  />
 Added: Support files for Arm Compiler v6 (cmsis_armcc_v6.h).   </td></tr>
<tr>
<td>V4.20 </td><td>Corrected: MISRA-C:2004 violations. <br  />
 Corrected: predefined macro for TI CCS Compiler. <br  />
 Corrected: function <a class="el" href="group__intrinsic__SIMD__gr.html#ga15d8899a173effb8ad8c7268da32b60e">__SHADD16</a> in arm_math.h. <br  />
 Updated: cache functions for Cortex-M7. <br  />
 Added: macros <a class="el" href="Ref__Peripheral_8txt.html#a286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>, <a class="el" href="Ref__Peripheral_8txt.html#a139b6e261c981f014f386927ca4a8444">_FLD2VAL</a> to core_*.h. <br  />
 Updated: functions <a class="el" href="group__intrinsic__SIMD__gr.html#ga87618799672e1511e33964bc71467eb3">__QASX</a>, <a class="el" href="group__intrinsic__SIMD__gr.html#gab41eb2b17512ab01d476fc9d5bd19520">__QSAX</a>, <a class="el" href="group__intrinsic__SIMD__gr.html#gae0a649035f67627464fd80e7218c89d5">__SHASX</a>, <a class="el" href="group__intrinsic__SIMD__gr.html#gafadbd89c36b5addcf1ca10dd392db3e9">__SHSAX</a>. <br  />
 Corrected: potential bug in function <a class="el" href="group__intrinsic__SIMD__gr.html#ga15d8899a173effb8ad8c7268da32b60e">__SHADD16</a>.   </td></tr>
<tr>
<td>V4.10 </td><td>Corrected: MISRA-C:2004 violations. <br  />
 Corrected: intrinsic functions <a class="el" href="group__intrinsic__CPU__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">__DSB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gab1c9b393641dc2d397b3408fdbe72b96">__DMB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga93c09b4709394d81977300d5f84950e5">__ISB</a>. <br  />
 Corrected: register definitions for ITCMCR register. <br  />
 Corrected: register definitions for <a class="el" href="unionCONTROL__Type.html">CONTROL_Type</a> register. <br  />
 Added: functions <a class="el" href="group__fpu__functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756">SCB_GetFPUType</a>, <a class="el" href="group__Dcache__functions__m7.html#ga503ef7ef58c0773defd15a82f6336c09">SCB_InvalidateDCache_by_Addr</a> to core_cm7.h. <br  />
 Added: register definitions for <a class="el" href="unionAPSR__Type.html">APSR_Type</a>, <a class="el" href="unionIPSR__Type.html">IPSR_Type</a>, <a class="el" href="unionxPSR__Type.html">xPSR_Type</a> register. <br  />
 Added: <a class="el" href="group__Core__Register__gr.html#ga62fa63d39cf22df348857d5f44ab64d9">__set_BASEPRI_MAX</a> function to core_cmFunc.h. <br  />
 Added: intrinsic functions <a class="el" href="group__intrinsic__CPU__gr.html#gad6f9f297f6b91a995ee199fbc796b863">__RBIT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga90884c591ac5d73d6069334eba9d6c02">__CLZ</a> for Cortex-M0/CortexM0+. <br  />
   </td></tr>
<tr>
<td>V4.00 </td><td>Added: Cortex-M7 support.<br  />
 Added: intrinsic functions for <a class="el" href="group__intrinsic__CPU__gr.html#gac09134f1bf9c49db07282001afcc9380">__RRX</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga9464d75db32846aa8295c3c3adfacb41">__LDRBT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gaa762b8bc5634ce38cb14d62a6b2aee32">__LDRHT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga616504f5da979ba8a073d428d6e8d5c7">__LDRT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gad41aa59c92c0a165b7f98428d3320cd5">__STRBT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga2b5d93b8e461755b1072a03df3f1722e">__STRHT</a>, and <a class="el" href="group__intrinsic__CPU__gr.html#ga625bc4ac0b1d50de9bcd13d9f050030e">__STRT</a> <br  />
   </td></tr>
<tr>
<td>V3.40 </td><td>Corrected: C++ include guard settings.<br  />
  </td></tr>
<tr>
<td>V3.30 </td><td>Added: COSMIC tool chain support.<br  />
 Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.<br  />
 Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.<br  />
 Corrected: GCC/CLang warnings.<br  />
   </td></tr>
<tr>
<td>V3.20 </td><td>Added: <a class="el" href="group__intrinsic__CPU__gr.html#ga92f5621626711931da71eaa8bf301af7">__BKPT</a> instruction intrinsic.<br  />
 Added: <a class="el" href="group__intrinsic__SIMD__gr.html#gaea60757232f740ec6b09980eebb614ff">__SMMLA</a> instruction intrinsic for Cortex-M4.<br  />
 Corrected: ITM_SendChar.<br  />
 Corrected: <a class="el" href="group__Core__Register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">__enable_irq</a>, <a class="el" href="group__Core__Register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">__disable_irq</a> and inline assembly for GCC Compiler.<br  />
 Corrected: <a class="el" href="group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">NVIC_GetPriority</a> and VTOR_TBLOFF for Cortex-M0/M0+, SC000. <br  />
 Corrected: rework of in-line assembly functions to remove potential compiler warnings.<br  />
   </td></tr>
<tr>
<td>V3.01 </td><td>Added support for Cortex-M0+ processor.<br  />
  </td></tr>
<tr>
<td>V3.00 </td><td>Added support for GNU GCC ARM Embedded Compiler. <br  />
 Added function __ROR.<br  />
 Added <a class="el" href="regMap_pg.html">Register Mapping</a> for TPIU, DWT. <br  />
 Added support for <a class="el" href="device_h_pg.html#core_config_sect">SC000 and SC300 processors</a>.<br  />
 Corrected <a class="el" href="group__ITM__Debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a> function. <br  />
 Corrected the functions <a class="el" href="group__intrinsic__CPU__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a> for the GNU GCC compiler section. <br  />
 Documentation restructured.   </td></tr>
<tr>
<td>V2.10 </td><td>Updated documentation.<br  />
 Updated CMSIS core include files.<br  />
 Changed CMSIS/Device folder structure.<br  />
 Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.<br  />
 Reworked CMSIS DSP library examples.   </td></tr>
<tr>
<td>V2.00 </td><td>Added support for Cortex-M4 processor.  </td></tr>
<tr>
<td>V1.30 </td><td>Reworked Startup Concept.<br  />
 Added additional Debug Functionality.<br  />
 Changed folder structure.<br  />
 Added doxygen comments.<br  />
 Added definitions for bit.   </td></tr>
<tr>
<td>V1.01 </td><td>Added support for Cortex-M0 processor.  </td></tr>
<tr>
<td>V1.01 </td><td>Added intrinsic functions for <a class="el" href="group__intrinsic__CPU__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e">__LDREXB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga9feffc093d6f68b120d592a7a0d45a15">__LDREXH</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gabd78840a0f2464905b7cec791ebc6a4c">__LDREXW</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a>, and <a class="el" href="group__intrinsic__CPU__gr.html#ga354c5ac8870cc3dfb823367af9c4b412">__CLREX</a>  </td></tr>
<tr>
<td>V1.00 </td><td>Initial Release for Cortex-M3 processor.  </td></tr>
</table>
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</div><!-- PageDoc -->
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<div class="ttc" id="astructITM__Type_html_acd03c6858f7b678dab6a6121462e7807"><div class="ttname"><a href="structITM__Type.html#acd03c6858f7b678dab6a6121462e7807">ITM_Type::TER</a></div><div class="ttdeci">__IOM uint32_t TER</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:167</div></div>
<div class="ttc" id="agroup__system__init__gr_html_gae0c36a9591fe6e9c45ecb21a794f0f0f"><div class="ttname"><a href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">SystemCoreClockUpdate</a></div><div class="ttdeci">void SystemCoreClockUpdate(void)</div><div class="ttdoc">Function to update the variable SystemCoreClock.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga9c286d330f4fb29b256335add91eec9f"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga9c286d330f4fb29b256335add91eec9f">__SMLADX</a></div><div class="ttdeci">uint32_t __SMLADX(uint32_t val1, uint32_t val2, uint32_t val3)</div><div class="ttdoc">Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator.</div></div>
<div class="ttc" id="astructMPU__Type_html_af8b510a85b175edfd8dd8cc93e967066"><div class="ttname"><a href="structMPU__Type.html#af8b510a85b175edfd8dd8cc93e967066">MPU_Type::RBAR_A1</a></div><div class="ttdeci">__IOM uint32_t RBAR_A1</div><div class="ttdoc">Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:207</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gae0a649035f67627464fd80e7218c89d5"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gae0a649035f67627464fd80e7218c89d5">__SHASX</a></div><div class="ttdeci">uint32_t __SHASX(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Dual 16-bit signed addition and subtraction with halved results.</div></div>
<div class="ttc" id="agroup__compiler__conntrol__gr_html_gade2d8d7118f8ff49547f60aa0c3382bb"><div class="ttname"><a href="group__compiler__conntrol__gr.html#gade2d8d7118f8ff49547f60aa0c3382bb">__INLINE</a></div><div class="ttdeci">#define __INLINE</div><div class="ttdoc">Recommend that function should be inlined by the compiler.</div><div class="ttdef"><b>Definition:</b> Ref_CompilerControl.txt:109</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga3ba259f8f05a36f7b88b469a71ffc096"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga3ba259f8f05a36f7b88b469a71ffc096">__QSUB</a></div><div class="ttdeci">uint32_t __QSUB(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Q setting saturating subtract.</div></div>
<div class="ttc" id="astructDWT__Type_html_a52d4ff278fae6f9216c63b74ce328841"><div class="ttname"><a href="structDWT__Type.html#a52d4ff278fae6f9216c63b74ce328841">DWT_Type::FUNCTION3</a></div><div class="ttdeci">__IOM uint32_t FUNCTION3</div><div class="ttdoc">Offset: 0x058 (R/W) Function Register 3.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:269</div></div>
<div class="ttc" id="agroup__coreregister__trustzone__functions_html_ga41c3ac2d9af23c40647c053ad7d564e7"><div class="ttname"><a href="group__coreregister__trustzone__functions.html#ga41c3ac2d9af23c40647c053ad7d564e7">__TZ_set_MSP_NS</a></div><div class="ttdeci">void __TZ_set_MSP_NS(uint32_t topOfMainStack)</div><div class="ttdoc">Set Main Stack Pointer (non-secure)</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_gac2f1c567950e3785d75773362b525390"><div class="ttname"><a href="group__mpu8__functions.html#gac2f1c567950e3785d75773362b525390">ARM_MPU_ATTR_MEMORY_</a></div><div class="ttdeci">#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA)</div><div class="ttdoc">Attribute for normal memory (outer and inner)</div><div class="ttdef"><b>Definition:</b> Ref_MPU8.txt:47</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_gab5b3c0a53d19c09a5550f1d9071ae65c"><div class="ttname"><a href="group__mpu8__functions.html#gab5b3c0a53d19c09a5550f1d9071ae65c">ARM_MPU_SetMemAttr</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga9feffc093d6f68b120d592a7a0d45a15"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga9feffc093d6f68b120d592a7a0d45a15">__LDREXH</a></div><div class="ttdeci">uint16_t __LDREXH(volatile uint16_t *addr)</div><div class="ttdoc">LDR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="aunionxPSR__Type_html_a7eed9fe24ae8d354cd76ae1c1110a658"><div class="ttname"><a href="unionxPSR__Type.html#a7eed9fe24ae8d354cd76ae1c1110a658">xPSR_Type::T</a></div><div class="ttdeci">uint32_t T</div><div class="ttdoc">bit: 24 Thumb bit (read 0)</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:54</div></div>
<div class="ttc" id="astructSCB__Type_html_a187a4578e920544ed967f98020fb8170"><div class="ttname"><a href="structSCB__Type.html#a187a4578e920544ed967f98020fb8170">SCB_Type::VTOR</a></div><div class="ttdeci">__IOM uint32_t VTOR</div><div class="ttdoc">Offset: 0x008 (R/W) Vector Table Offset Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:110</div></div>
<div class="ttc" id="astructTPI__Type_html_aa4d7b5cf39dff9f53bf7f69bc287a814"><div class="ttname"><a href="structTPI__Type.html#aa4d7b5cf39dff9f53bf7f69bc287a814">TPI_Type::FIFO0</a></div><div class="ttdeci">__IM uint32_t FIFO0</div><div class="ttdoc">Offset: 0xEEC (R/ ) Integration ETM Data.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:290</div></div>
<div class="ttc" id="agroup__nvic__trustzone__functions_html_gaccbc9aa0eacf4d4c3d3046edb9e02edd"><div class="ttname"><a href="group__nvic__trustzone__functions.html#gaccbc9aa0eacf4d4c3d3046edb9e02edd">TZ_NVIC_SetPendingIRQ_NS</a></div><div class="ttdeci">void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)</div><div class="ttdoc">Set Pending Interrupt (non-secure)</div></div>
<div class="ttc" id="astructSCB__Type_html_a0cda9e061b42373383418663092ad19a"><div class="ttname"><a href="structSCB__Type.html#a0cda9e061b42373383418663092ad19a">SCB_Type::CFSR</a></div><div class="ttdeci">__IOM uint32_t CFSR</div><div class="ttdoc">Offset: 0x028 (R/W) Configurable Fault Status Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:116</div></div>
<div class="ttc" id="astructITM__Type_html_ae907229ba50538bf370fbdfd54c099a2"><div class="ttname"><a href="structITM__Type.html#ae907229ba50538bf370fbdfd54c099a2">ITM_Type::TPR</a></div><div class="ttdeci">__IOM uint32_t TPR</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:169</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga22a24f416b65c2f5a82d9f1162d9394d"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga22a24f416b65c2f5a82d9f1162d9394d">__LDA</a></div><div class="ttdeci">uint32_t __LDA(volatile uint32_t *ptr)</div><div class="ttdoc">Load-Acquire (32 bit)</div></div>
<div class="ttc" id="astructSCB__Type_html_a7b5ae9741a99808043394c4743b635c4"><div class="ttname"><a href="structSCB__Type.html#a7b5ae9741a99808043394c4743b635c4">SCB_Type::SHCSR</a></div><div class="ttdeci">__IOM uint32_t SHCSR</div><div class="ttdoc">Offset: 0x024 (R/W) System Handler Control and State Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:115</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_gaeef6f853b6df3a365c838ee5b49a7a26"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#gaeef6f853b6df3a365c838ee5b49a7a26">__REV16</a></div><div class="ttdeci">uint32_t __REV16(uint32_t value)</div><div class="ttdoc">Reverse byte order (16 bit)</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gafadbd89c36b5addcf1ca10dd392db3e9"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gafadbd89c36b5addcf1ca10dd392db3e9">__SHSAX</a></div><div class="ttdeci">uint32_t __SHSAX(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Dual 16-bit signed subtraction and addition with halved results.</div></div>
<div class="ttc" id="astructSCB__Type_html_af084e1b2dad004a88668efea1dfe7fa1"><div class="ttname"><a href="structSCB__Type.html#af084e1b2dad004a88668efea1dfe7fa1">SCB_Type::ADR</a></div><div class="ttdeci">__IM uint32_t ADR</div><div class="ttdoc">Offset: 0x04C (R/ ) Auxiliary Feature Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:124</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga039142a5368840683cf329cb55b73f84"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga039142a5368840683cf329cb55b73f84">__SMUSD</a></div><div class="ttdeci">uint32_t __SMUSD(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Dual 16-bit signed multiply returning difference.</div></div>
<div class="ttc" id="agroup__nvic__trustzone__functions_html_gab85bd0d55d746caf0e414be5284afe24"><div class="ttname"><a href="group__nvic__trustzone__functions.html#gab85bd0d55d746caf0e414be5284afe24">TZ_NVIC_GetPendingIRQ_NS</a></div><div class="ttdeci">uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)</div><div class="ttdoc">Get Pending Interrupt (non-secure)</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gga666eb0caeb12ec0e281415592ae89083a33ff1cf7098de65d61b6354fee6cd5aa"><div class="ttname"><a href="group__NVIC__gr.html#gga666eb0caeb12ec0e281415592ae89083a33ff1cf7098de65d61b6354fee6cd5aa">MemoryManagement_IRQn</a></div><div class="ttdeci">@ MemoryManagement_IRQn</div><div class="ttdoc">Exception 4: Memory Management Interrupt [not on Cortex-M0 variants].</div><div class="ttdef"><b>Definition:</b> Ref_NVIC.txt:389</div></div>
<div class="ttc" id="astructDWT__Type_html_a6353ca1d1ad9bc1be05d3b5632960113"><div class="ttname"><a href="structDWT__Type.html#a6353ca1d1ad9bc1be05d3b5632960113">DWT_Type::PCSR</a></div><div class="ttdeci">__IM uint32_t PCSR</div><div class="ttdoc">Offset: 0x01C (R/ ) Program Counter Sample Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:254</div></div>
<div class="ttc" id="astructDWT__Type_html_a5ae6dde39989f27bae90afc2347deb46"><div class="ttname"><a href="structDWT__Type.html#a5ae6dde39989f27bae90afc2347deb46">DWT_Type::COMP2</a></div><div class="ttdeci">__IOM uint32_t COMP2</div><div class="ttdoc">Offset: 0x040 (R/W) Comparator Register 2.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:263</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gad0bf46373a1c05aabf64517e84be5984"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gad0bf46373a1c05aabf64517e84be5984">__SADD16</a></div><div class="ttdeci">uint32_t __SADD16(uint32_t val1, uint32_t val2)</div><div class="ttdoc">GE setting dual 16-bit signed addition.</div></div>
<div class="ttc" id="agroup__context__trustzone__functions_html_gacd016f166bee549a0d3e970132e64a90"><div class="ttname"><a href="group__context__trustzone__functions.html#gacd016f166bee549a0d3e970132e64a90">TZ_AllocModuleContext_S</a></div><div class="ttdeci">TZ_MemoryId_t TZ_AllocModuleContext_S(TZ_ModuleId_t module)</div><div class="ttdoc">Allocate context memory for calling secure software modules in TrustZone.</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_gaed91dfbf3d7d7b7fba8d912fcbeaad88"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#gaed91dfbf3d7d7b7fba8d912fcbeaad88">__WFI</a></div><div class="ttdeci">void __WFI(void)</div><div class="ttdoc">Wait For Interrupt.</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_gac09134f1bf9c49db07282001afcc9380"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#gac09134f1bf9c49db07282001afcc9380">__RRX</a></div><div class="ttdeci">uint32_t __RRX(uint32_t value)</div><div class="ttdoc">Rotate Right with Extend (32 bit)</div></div>
<div class="ttc" id="agroup__mpu__functions_html_ga9dcb0afddf4ac351f33f3c7a5169c62c"><div class="ttname"><a href="group__mpu__functions.html#ga9dcb0afddf4ac351f33f3c7a5169c62c">ARM_MPU_ClrRegion</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga4717abc17af5ba29b1e4c055e0a0d9b8"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga4717abc17af5ba29b1e4c055e0a0d9b8">__REV</a></div><div class="ttdeci">uint32_t __REV(uint32_t value)</div><div class="ttdoc">Reverse byte order (32 bit)</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga799b5d9a2ae75e459264c8512c7c0e02"><div class="ttname"><a href="group__Core__Register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02">__get_PRIMASK</a></div><div class="ttdeci">uint32_t __get_PRIMASK(void)</div><div class="ttdoc">Read the PRIMASK register bit.</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga3c74d923529f664eda099d1b2668b3c1"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga3c74d923529f664eda099d1b2668b3c1">__LDAEX</a></div><div class="ttdeci">uint32_t __LDAEX(volatile uint32_t *ptr)</div><div class="ttdoc">Load-Acquire Exclusive (32 bit)</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gad80e9b20c1736fd798f897362273a146"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gad80e9b20c1736fd798f897362273a146">__SMLALD</a></div><div class="ttdeci">uint64_t __SMLALD(uint32_t val1, uint32_t val2, uint64_t val3)</div><div class="ttdoc">Dual 16-bit signed multiply with single 64-bit accumulator.</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_gafe39c2f98058bcac7e7e0501e64e7a9d"><div class="ttname"><a href="group__mpu8__functions.html#gafe39c2f98058bcac7e7e0501e64e7a9d">ARM_MPU_RBAR</a></div><div class="ttdeci">#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN)</div><div class="ttdoc">Region Base Address Register value.</div><div class="ttdef"><b>Definition:</b> Ref_MPU8.txt:89</div></div>
<div class="ttc" id="aunionAPSR__Type_html_a7e7bbba9b00b0bb3283dc07f1abe37e0"><div class="ttname"><a href="unionAPSR__Type.html#a7e7bbba9b00b0bb3283dc07f1abe37e0">APSR_Type::N</a></div><div class="ttdeci">uint32_t N</div><div class="ttdoc">bit: 31 Negative condition code flag</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:19</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gaf2f5a9132dcfc6d01d34cd971c425713"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gaf2f5a9132dcfc6d01d34cd971c425713">__QADD8</a></div><div class="ttdeci">uint32_t __QADD8(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Q setting quad 8-bit saturating addition.</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga616504f5da979ba8a073d428d6e8d5c7"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga616504f5da979ba8a073d428d6e8d5c7">__LDRT</a></div><div class="ttdeci">uint32_t __LDRT(uint32_t ptr)</div><div class="ttdoc">LDRT Unprivileged (32 bit)</div></div>
<div class="ttc" id="astructITM__Type_html_ab4a4cc97ad658e9c46cf17490daffb8a"><div class="ttname"><a href="structITM__Type.html#ab4a4cc97ad658e9c46cf17490daffb8a">ITM_Type::PID0</a></div><div class="ttdeci">__IM uint32_t PID0</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:186</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_ga01fa1151c9ec0ba5de76f908c0999316"><div class="ttname"><a href="group__mpu8__functions.html#ga01fa1151c9ec0ba5de76f908c0999316">ARM_MPU_ClrRegionEx</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type *mpu, uint32_t rnr)</div></div>
<div class="ttc" id="agroup__Icache__functions__m7_html_ga50d373a785edd782c5de5a3b55e30ff3"><div class="ttname"><a href="group__Icache__functions__m7.html#ga50d373a785edd782c5de5a3b55e30ff3">SCB_InvalidateICache</a></div><div class="ttdeci">__STATIC_INLINE void SCB_InvalidateICache(void)</div><div class="ttdoc">Invalidate I-Cache.</div></div>
<div class="ttc" id="agroup__systick__trustzone__functions_html_gad18a1b1a6796c652f2b35e728f2e2670"><div class="ttname"><a href="group__systick__trustzone__functions.html#gad18a1b1a6796c652f2b35e728f2e2670">TZ_SysTick_Config_NS</a></div><div class="ttdeci">uint32_t TZ_SysTick_Config_NS(uint32_t ticks)</div><div class="ttdoc">System Tick Configuration (non-secure)</div></div>
<div class="ttc" id="astructMPU__Type_html_a37131c513d8a8d211b402e5dfda97205"><div class="ttname"><a href="structMPU__Type.html#a37131c513d8a8d211b402e5dfda97205">MPU_Type::RASR_A2</a></div><div class="ttdeci">__IOM uint32_t RASR_A2</div><div class="ttdoc">Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:210</div></div>
<div class="ttc" id="astructCoreDebug__Type_html_af907cf64577eaf927dac6787df6dd98b"><div class="ttname"><a href="structCoreDebug__Type.html#af907cf64577eaf927dac6787df6dd98b">CoreDebug_Type::DCRSR</a></div><div class="ttdeci">__OM uint32_t DCRSR</div><div class="ttdoc">Offset: 0x004 ( /W) Debug Core Register Selector Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:236</div></div>
<div class="ttc" id="agroup__coreregister__trustzone__functions_html_ga40ff8336c6d09af6da1081d4e4adc126"><div class="ttname"><a href="group__coreregister__trustzone__functions.html#ga40ff8336c6d09af6da1081d4e4adc126">__TZ_get_PSP_NS</a></div><div class="ttdeci">uint32_t __TZ_get_PSP_NS(void)</div><div class="ttdoc">Get Process Stack Pointer (non-secure)</div></div>
<div class="ttc" id="aunionCONTROL__Type_html_a6b642cca3d96da660b1198c133ca2a1f"><div class="ttname"><a href="unionCONTROL__Type.html#a6b642cca3d96da660b1198c133ca2a1f">CONTROL_Type::w</a></div><div class="ttdeci">uint32_t w</div><div class="ttdoc">Type used for word access.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:78</div></div>
<div class="ttc" id="astructITM__Type_html_ac40df2c3a6cef02f90b4e82c8204756f"><div class="ttname"><a href="structITM__Type.html#ac40df2c3a6cef02f90b4e82c8204756f">ITM_Type::CID1</a></div><div class="ttdeci">__IM uint32_t CID1</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:191</div></div>
<div class="ttc" id="aunionxPSR__Type_html"><div class="ttname"><a href="unionxPSR__Type.html">xPSR_Type</a></div><div class="ttdoc">Union type to access the Special-Purpose Program Status Registers (xPSR).</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:42</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga4348d14fc5eefbfd34ab8c51be44a81b"><div class="ttname"><a href="group__Core__Register__gr.html#ga4348d14fc5eefbfd34ab8c51be44a81b">__set_PSPLIM</a></div><div class="ttdeci">void __set_PSPLIM(uint32_t ProcStackPtrLimit)</div><div class="ttdoc">Set Process Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the no...</div></div>
<div class="ttc" id="agroup__compiler__conntrol__gr_html_ga378ac21329d33f561f90265eef89f564"><div class="ttname"><a href="group__compiler__conntrol__gr.html#ga378ac21329d33f561f90265eef89f564">__RESTRICT</a></div><div class="ttdeci">#define __RESTRICT</div><div class="ttdoc">restrict pointer qualifier to enable additional optimizations.</div><div class="ttdef"><b>Definition:</b> Ref_CompilerControl.txt:199</div></div>
<div class="ttc" id="astructDWT__Type_html_a1cfc48384ebd8fd8fb7e5d955aae6c97"><div class="ttname"><a href="structDWT__Type.html#a1cfc48384ebd8fd8fb7e5d955aae6c97">DWT_Type::FOLDCNT</a></div><div class="ttdeci">__IOM uint32_t FOLDCNT</div><div class="ttdoc">Offset: 0x018 (R/W) Folded-instruction Count Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:253</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga95e666b82216066bf6064d1244e6883c"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga95e666b82216066bf6064d1244e6883c">__SSAT16</a></div><div class="ttdeci">uint32_t __SSAT16(uint32_t val1, const uint32_t val2)</div><div class="ttdoc">Q setting dual 16-bit saturate.</div></div>
<div class="ttc" id="astructITM__Type_html_aad5e11dd4baf6d941bd6c7450f60a158"><div class="ttname"><a href="structITM__Type.html#aad5e11dd4baf6d941bd6c7450f60a158">ITM_Type::PID4</a></div><div class="ttdeci">__IM uint32_t PID4</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:182</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga09e129e6613329aab87c89f1108b7ed7"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga09e129e6613329aab87c89f1108b7ed7">__UHSAX</a></div><div class="ttdeci">uint32_t __UHSAX(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Dual 16-bit unsigned subtraction and addition with halved results and exchange.</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gad01d3aa220b50ef141b06c93888b268d"><div class="ttname"><a href="group__NVIC__gr.html#gad01d3aa220b50ef141b06c93888b268d">CMSIS_VECTAB_VIRTUAL</a></div><div class="ttdeci">#define CMSIS_VECTAB_VIRTUAL</div><div class="ttdoc">Virtualization of interrupt vector table access functions.</div></div>
<div class="ttc" id="astructMPU__Type_html_a2f7a117a12cb661c76edc4765453f05c"><div class="ttname"><a href="structMPU__Type.html#a2f7a117a12cb661c76edc4765453f05c">MPU_Type::RNR</a></div><div class="ttdeci">__IOM uint32_t RNR</div><div class="ttdoc">Offset: 0x008 (R/W) MPU Region RNRber Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:204</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gaf46218d01a6a3b70666ad0492a7f950a"><div class="ttname"><a href="group__NVIC__gr.html#gaf46218d01a6a3b70666ad0492a7f950a">NVIC_SetTargetState</a></div><div class="ttdeci">uint32_t NVIC_SetTargetState(IRQn_Type IRQn)</div><div class="ttdoc">Set Interrupt Target State.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gad032bd21f013c5d29f5fcb6b0f02bc3f"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gad032bd21f013c5d29f5fcb6b0f02bc3f">__USADA8</a></div><div class="ttdeci">uint32_t __USADA8(uint32_t val1, uint32_t val2, uint32_t val3)</div><div class="ttdoc">Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate.</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_ga5a3f40314553baccdeea551f86d9a997"><div class="ttname"><a href="group__mpu8__functions.html#ga5a3f40314553baccdeea551f86d9a997">ARM_MPU_Enable</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)</div></div>
<div class="ttc" id="astructITM__Type_html_ad34dbe6b1072c77d36281049c8b169f6"><div class="ttname"><a href="structITM__Type.html#ad34dbe6b1072c77d36281049c8b169f6">ITM_Type::PID6</a></div><div class="ttdeci">__IM uint32_t PID6</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:184</div></div>
<div class="ttc" id="agroup__Dcache__functions__m7_html_ga55583e3065c6eabca204b8b89b121c4c"><div class="ttname"><a href="group__Dcache__functions__m7.html#ga55583e3065c6eabca204b8b89b121c4c">SCB_CleanDCache</a></div><div class="ttdeci">__STATIC_INLINE void SCB_CleanDCache(void)</div><div class="ttdoc">Clean D-Cache.</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga9d174f979b2f76fdb3228a9b338fd939"><div class="ttname"><a href="group__Core__Register__gr.html#ga9d174f979b2f76fdb3228a9b338fd939">__disable_fault_irq</a></div><div class="ttdeci">void __disable_fault_irq(void)</div><div class="ttdoc">Disables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga83e69ef81057d3cbd06863d729385187"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga83e69ef81057d3cbd06863d729385187">__SMLSLDX</a></div><div class="ttdeci">unsigned long long __SMLSLDX(uint32_t val1, uint32_t val2, unsigned long long val3)</div><div class="ttdoc">Q setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate.</div></div>
<div class="ttc" id="agroup__coreregister__trustzone__functions_html_gaaaf2aaf904b25ed17fd3e5e63f8e029b"><div class="ttname"><a href="group__coreregister__trustzone__functions.html#gaaaf2aaf904b25ed17fd3e5e63f8e029b">__TZ_get_SP_NS</a></div><div class="ttdeci">uint32_t __TZ_get_SP_NS(void)</div><div class="ttdoc">Get Stack Pointer (non-secure)</div></div>
<div class="ttc" id="astructMPU__Type_html_a207f6e9c3af753367554cc06df300a55"><div class="ttname"><a href="structMPU__Type.html#a207f6e9c3af753367554cc06df300a55">MPU_Type::RBAR_A3</a></div><div class="ttdeci">__IOM uint32_t RBAR_A3</div><div class="ttdoc">Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:211</div></div>
<div class="ttc" id="aunionAPSR__Type_html"><div class="ttname"><a href="unionAPSR__Type.html">APSR_Type</a></div><div class="ttdoc">Union type to access the Application Program Status Register (APSR).</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:4</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga354c5ac8870cc3dfb823367af9c4b412"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga354c5ac8870cc3dfb823367af9c4b412">__CLREX</a></div><div class="ttdeci">void __CLREX(void)</div><div class="ttdoc">Remove the exclusive lock [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="agroup__coreregister__trustzone__functions_html_gad2013f4d4311d6db253594a12d192617"><div class="ttname"><a href="group__coreregister__trustzone__functions.html#gad2013f4d4311d6db253594a12d192617">__TZ_set_MSPLIM_NS</a></div><div class="ttdeci">void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)</div><div class="ttdoc">Set Main Stack Pointer Limit (non-secure) Devices without Armv8-M Main Extensions (i....</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gga666eb0caeb12ec0e281415592ae89083aa62e040960b4beb6cba107e4703c12d2"><div class="ttname"><a href="group__NVIC__gr.html#gga666eb0caeb12ec0e281415592ae89083aa62e040960b4beb6cba107e4703c12d2">WWDG_STM_IRQn</a></div><div class="ttdeci">@ WWDG_STM_IRQn</div><div class="ttdoc">Device Interrupt 0: Window WatchDog Interrupt.</div><div class="ttdef"><b>Definition:</b> Ref_NVIC.txt:400</div></div>
<div class="ttc" id="astructITM__Type_html"><div class="ttname"><a href="structITM__Type.html">ITM_Type</a></div><div class="ttdoc">Structure type to access the Instrumentation Trace Macrocell Register (ITM).</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:158</div></div>
<div class="ttc" id="agroup__Dcache__functions__m7_html_ga630131b2572eaa16b569ed364dfc895e"><div class="ttname"><a href="group__Dcache__functions__m7.html#ga630131b2572eaa16b569ed364dfc895e">SCB_CleanInvalidateDCache_by_Addr</a></div><div class="ttdeci">__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize)</div><div class="ttdoc">D-Cache Clean and Invalidate by address.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gac20aa0f741d0a1494d58c531e38d5785"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gac20aa0f741d0a1494d58c531e38d5785">__SADD8</a></div><div class="ttdeci">uint32_t __SADD8(uint32_t val1, uint32_t val2)</div><div class="ttdoc">GE setting quad 8-bit signed addition.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gaba63bb52e1e93fb527e26f3d474da12e"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gaba63bb52e1e93fb527e26f3d474da12e">__SSUB8</a></div><div class="ttdeci">uint32_t __SSUB8(uint32_t val1, uint32_t val2)</div><div class="ttdoc">GE setting quad 8-bit signed subtraction.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gae83a53ec04b496304bed6d9fe8f7461b"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gae83a53ec04b496304bed6d9fe8f7461b">__QADD16</a></div><div class="ttdeci">uint32_t __QADD16(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Q setting dual 16-bit saturating addition.</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga0f98dfbd252b89d12564472dbeba9c27"><div class="ttname"><a href="group__Core__Register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">__enable_irq</a></div><div class="ttdeci">void __enable_irq(void)</div><div class="ttdoc">Globally enables interrupts and configurable fault handlers.</div></div>
<div class="ttc" id="agroup__coreregister__trustzone__functions_html_ga81e0995ee0fd2a9dcd9e9681bc22c76f"><div class="ttname"><a href="group__coreregister__trustzone__functions.html#ga81e0995ee0fd2a9dcd9e9681bc22c76f">__TZ_set_PSPLIM_NS</a></div><div class="ttdeci">void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)</div><div class="ttdoc">Set Process Stack Pointer (non-secure) Devices without Armv8-M Main Extensions (i....</div></div>
<div class="ttc" id="agroup__Icache__functions__m7_html_gaf9e7c6c8e16ada1f95e5bf5a03505b68"><div class="ttname"><a href="group__Icache__functions__m7.html#gaf9e7c6c8e16ada1f95e5bf5a03505b68">SCB_EnableICache</a></div><div class="ttdeci">__STATIC_INLINE void SCB_EnableICache(void)</div><div class="ttdoc">Enable I-Cache.</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gga666eb0caeb12ec0e281415592ae89083ab1a222a34a32f0ef5ac65e714efc1f85"><div class="ttname"><a href="group__NVIC__gr.html#gga666eb0caeb12ec0e281415592ae89083ab1a222a34a32f0ef5ac65e714efc1f85">HardFault_IRQn</a></div><div class="ttdeci">@ HardFault_IRQn</div><div class="ttdoc">Exception 3: Hard Fault Interrupt.</div><div class="ttdef"><b>Definition:</b> Ref_NVIC.txt:388</div></div>
<div class="ttc" id="aunionIPSR__Type_html_a4adca999d3a0bc1ae682d73ea7cfa879"><div class="ttname"><a href="unionIPSR__Type.html#a4adca999d3a0bc1ae682d73ea7cfa879">IPSR_Type::w</a></div><div class="ttdeci">uint32_t w</div><div class="ttdoc">Type used for word access.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:35</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gaefb8ebf3a54e197464da1ff69a44f4b5"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gaefb8ebf3a54e197464da1ff69a44f4b5">__PKHBT</a></div><div class="ttdeci">uint32_t __PKHBT(uint32_t val1, uint32_t val2, uint32_t val3)</div><div class="ttdoc">Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] of val2 levitated with the...</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga5845084fd99c872e98cf5553d554de2a"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga5845084fd99c872e98cf5553d554de2a">__SASX</a></div><div class="ttdeci">uint32_t __SASX(uint32_t val1, uint32_t val2)</div><div class="ttdoc">GE setting dual 16-bit addition and subtraction with exchange.</div></div>
<div class="ttc" id="agroup__mpu__functions_html_ga7cbc0a4a066ed90e85c8176228235d57"><div class="ttname"><a href="group__mpu__functions.html#ga7cbc0a4a066ed90e85c8176228235d57">ARM_MPU_Disable</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_Disable()</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga8b226929264e903c7019e326b42bef47"><div class="ttname"><a href="group__Core__Register__gr.html#ga8b226929264e903c7019e326b42bef47">__get_PSPLIM</a></div><div class="ttdeci">uint32_t __get_PSPLIM(void)</div><div class="ttdoc">Get Process Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the no...</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gab41d713653b16f8d9fef44d14e397228"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gab41d713653b16f8d9fef44d14e397228">__UXTB16</a></div><div class="ttdeci">uint32_t __UXTB16(uint32_t val)</div><div class="ttdoc">Dual extract 8-bits and zero-extend to 16-bits.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gabd0b0e2da2e6364e176d051687702b86"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gabd0b0e2da2e6364e176d051687702b86">__UHADD16</a></div><div class="ttdeci">uint32_t __UHADD16(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Dual 16-bit unsigned addition with halved results.</div></div>
<div class="ttc" id="astructDWT__Type_html_ab1b60d6600c38abae515bab8e86a188f"><div class="ttname"><a href="structDWT__Type.html#ab1b60d6600c38abae515bab8e86a188f">DWT_Type::FUNCTION2</a></div><div class="ttdeci">__IOM uint32_t FUNCTION2</div><div class="ttdoc">Offset: 0x048 (R/W) Function Register 2.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:265</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gafd8fe4a6d87e947caa81a69ec36c1666"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gafd8fe4a6d87e947caa81a69ec36c1666">__PKHTB</a></div><div class="ttdeci">uint32_t __PKHTB(uint32_t val1, uint32_t val2, uint32_t val3)</div><div class="ttdoc">Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] of val2 right-shifted with...</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gab41eb2b17512ab01d476fc9d5bd19520"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gab41eb2b17512ab01d476fc9d5bd19520">__QSAX</a></div><div class="ttdeci">uint32_t __QSAX(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Q setting dual 16-bit subtract and add with exchange.</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_gabd78840a0f2464905b7cec791ebc6a4c"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#gabd78840a0f2464905b7cec791ebc6a4c">__LDREXW</a></div><div class="ttdeci">uint32_t __LDREXW(volatile uint32_t *addr)</div><div class="ttdoc">LDR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="aunionCONTROL__Type_html_af8c314273a1e4970a5671bd7f8184f50"><div class="ttname"><a href="unionCONTROL__Type.html#af8c314273a1e4970a5671bd7f8184f50">CONTROL_Type::_reserved0</a></div><div class="ttdeci">uint32_t _reserved0</div><div class="ttdoc">bit: 3..31 Reserved</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:76</div></div>
<div class="ttc" id="astructTPI__Type_html_a061372fcd72f1eea871e2d9c1be849bc"><div class="ttname"><a href="structTPI__Type.html#a061372fcd72f1eea871e2d9c1be849bc">TPI_Type::FIFO1</a></div><div class="ttdeci">__IM uint32_t FIFO1</div><div class="ttdoc">Offset: 0xEFC (R/ ) Integration ITM Data.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:294</div></div>
<div class="ttc" id="astructARM__MPU__Region__t_html_afe7a7721aa08988d915670efa432cdd2"><div class="ttname"><a href="structARM__MPU__Region__t.html#afe7a7721aa08988d915670efa432cdd2">ARM_MPU_Region_t::RBAR</a></div><div class="ttdeci">uint32_t RBAR</div><div class="ttdoc">The region base address register value (RBAR)</div><div class="ttdef"><b>Definition:</b> Ref_MPU.txt:85</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gga666eb0caeb12ec0e281415592ae89083a4ce820b3cc6cf3a796b41aadc0cf1237"><div class="ttname"><a href="group__NVIC__gr.html#gga666eb0caeb12ec0e281415592ae89083a4ce820b3cc6cf3a796b41aadc0cf1237">SVCall_IRQn</a></div><div class="ttdeci">@ SVCall_IRQn</div><div class="ttdoc">Exception 11: SV Call Interrupt.</div><div class="ttdef"><b>Definition:</b> Ref_NVIC.txt:395</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga980353d2c72ebb879282e49f592fddc0"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga980353d2c72ebb879282e49f592fddc0">__UASX</a></div><div class="ttdeci">uint32_t __UASX(uint32_t val1, uint32_t val2)</div><div class="ttdoc">GE setting dual 16-bit unsigned addition and subtraction with exchange.</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_gac64d37e7ff9de06437f9fb94bbab8b6c"><div class="ttname"><a href="group__Core__Register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c">__set_CONTROL</a></div><div class="ttdeci">void __set_CONTROL(uint32_t control)</div><div class="ttdoc">Set the CONTROL Register.</div></div>
<div class="ttc" id="agroup__coreregister__trustzone__functions_html_ga5da646ec291b6a183f38497ce92be51c"><div class="ttname"><a href="group__coreregister__trustzone__functions.html#ga5da646ec291b6a183f38497ce92be51c">__TZ_get_PSPLIM_NS</a></div><div class="ttdeci">uint32_t __TZ_get_PSPLIM_NS(void)</div><div class="ttdoc">Get Process Stack Pointer Limit (non-secure) Devices without Armv8-M Main Extensions (i....</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gab43c1c59d5c081f1bc725237f4b1f916"><div class="ttname"><a href="group__NVIC__gr.html#gab43c1c59d5c081f1bc725237f4b1f916">NVIC_SetVector</a></div><div class="ttdeci">void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)</div><div class="ttdoc">Modify Interrupt Vector [not for Cortex-M0, SC000].</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gga666eb0caeb12ec0e281415592ae89083a6dbff8f8543325f3474cbae2446776e7"><div class="ttname"><a href="group__NVIC__gr.html#gga666eb0caeb12ec0e281415592ae89083a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a></div><div class="ttdeci">@ SysTick_IRQn</div><div class="ttdoc">Exception 15: System Tick Interrupt.</div><div class="ttdef"><b>Definition:</b> Ref_NVIC.txt:398</div></div>
<div class="ttc" id="astructITM__Type_html_aa9da04891e48d1a2f054de186e9c4c94"><div class="ttname"><a href="structITM__Type.html#aa9da04891e48d1a2f054de186e9c4c94">ITM_Type::IWR</a></div><div class="ttdeci">__OM uint32_t IWR</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:173</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga811c0012221ee918a75111ca84c4d5e7"><div class="ttname"><a href="group__Core__Register__gr.html#ga811c0012221ee918a75111ca84c4d5e7">__get_APSR</a></div><div class="ttdeci">uint32_t __get_APSR(void)</div><div class="ttdoc">Read the APSR register.</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gga666eb0caeb12ec0e281415592ae89083ade177d9c70c89e084093024b932a4e30"><div class="ttname"><a href="group__NVIC__gr.html#gga666eb0caeb12ec0e281415592ae89083ade177d9c70c89e084093024b932a4e30">NonMaskableInt_IRQn</a></div><div class="ttdeci">@ NonMaskableInt_IRQn</div><div class="ttdoc">Exception 2: Non Maskable Interrupt.</div><div class="ttdef"><b>Definition:</b> Ref_NVIC.txt:387</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_gab1c9b393641dc2d397b3408fdbe72b96"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#gab1c9b393641dc2d397b3408fdbe72b96">__DMB</a></div><div class="ttdeci">void __DMB(void)</div><div class="ttdoc">Data Memory Barrier.</div></div>
<div class="ttc" id="aunionAPSR__Type_html_a86e2c5b891ecef1ab55b1edac0da79a6"><div class="ttname"><a href="unionAPSR__Type.html#a86e2c5b891ecef1ab55b1edac0da79a6">APSR_Type::C</a></div><div class="ttdeci">uint32_t C</div><div class="ttdoc">bit: 29 Carry condition code flag</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:17</div></div>
<div class="ttc" id="agroup__Dcache__functions__m7_html_ga1b741def9e3b2ca97dc9ea49b8ce505c"><div class="ttname"><a href="group__Dcache__functions__m7.html#ga1b741def9e3b2ca97dc9ea49b8ce505c">SCB_CleanInvalidateDCache</a></div><div class="ttdeci">__STATIC_INLINE void SCB_CleanInvalidateDCache(void)</div><div class="ttdoc">Clean &amp; Invalidate D-Cache.</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga0a354bdf71caa52f081a4a54e84c8d2a"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a></div><div class="ttdeci">uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)</div><div class="ttdoc">STR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="astructMPU__Type_html_aba02af87f77577c725cf73879cabb609"><div class="ttname"><a href="structMPU__Type.html#aba02af87f77577c725cf73879cabb609">MPU_Type::TYPE</a></div><div class="ttdeci">__IM uint32_t TYPE</div><div class="ttdoc">Offset: 0x000 (R/ ) MPU Type Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:202</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gad3cbca1be7a4726afa9448a9acd89377"><div class="ttname"><a href="group__NVIC__gr.html#gad3cbca1be7a4726afa9448a9acd89377">NVIC_DecodePriority</a></div><div class="ttdeci">void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)</div><div class="ttdoc">Decode the interrupt priority [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="agroup__mpu__functions_html_ga042ba1a6a1a58795231459ac0410b809"><div class="ttname"><a href="group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809">ARM_MPU_SetRegionEx</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)</div></div>
<div class="ttc" id="agroup__coreregister__trustzone__functions_html_ga624509c924d2583f0d4dca6ab270f051"><div class="ttname"><a href="group__coreregister__trustzone__functions.html#ga624509c924d2583f0d4dca6ab270f051">__TZ_get_BASEPRI_NS</a></div><div class="ttdeci">uint32_t __TZ_get_BASEPRI_NS(void)</div><div class="ttdoc">Get Base Priority (non-secure)</div></div>
<div class="ttc" id="astructDWT__Type_html_add790c53410023b3b581919bb681fe2a"><div class="ttname"><a href="structDWT__Type.html#add790c53410023b3b581919bb681fe2a">DWT_Type::CTRL</a></div><div class="ttdeci">__IOM uint32_t CTRL</div><div class="ttdoc">Offset: 0x000 (R/W) Control Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:247</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga1f7545b8dc33bb97982731cb9d427a69"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga1f7545b8dc33bb97982731cb9d427a69">__UHSUB16</a></div><div class="ttdeci">uint32_t __UHSUB16(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Dual 16-bit unsigned subtraction with halved results.</div></div>
<div class="ttc" id="aunionAPSR__Type_html_a3b04d58738b66a28ff13f23d8b0ba7e5"><div class="ttname"><a href="unionAPSR__Type.html#a3b04d58738b66a28ff13f23d8b0ba7e5">APSR_Type::Z</a></div><div class="ttdeci">uint32_t Z</div><div class="ttdoc">bit: 30 Zero condition code flag</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:18</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga524575b442ea01aec10c762bf4d85fea"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga524575b442ea01aec10c762bf4d85fea">__SHADD8</a></div><div class="ttdeci">uint32_t __SHADD8(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Quad 8-bit signed addition with halved results.</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga5429d7083fb8d30c43cecd3a861e1672"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga5429d7083fb8d30c43cecd3a861e1672">__STL</a></div><div class="ttdeci">void __STL(uint32_t value, volatile uint32_t *ptr)</div><div class="ttdoc">Store-Release (32 bit)</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga426b61640fc68f21b21ae4dc2726f3b4"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga426b61640fc68f21b21ae4dc2726f3b4">__LDAEXH</a></div><div class="ttdeci">uint16_t __LDAEXH(volatile uint32_t *ptr)</div><div class="ttdoc">Load-Acquire Exclusive (16 bit)</div></div>
<div class="ttc" id="agroup__coreregister__trustzone__functions_html_ga578b41087f207e1a475daae6cc8a28dc"><div class="ttname"><a href="group__coreregister__trustzone__functions.html#ga578b41087f207e1a475daae6cc8a28dc">__TZ_get_FAULTMASK_NS</a></div><div class="ttdeci">uint32_t __TZ_get_FAULTMASK_NS(void)</div><div class="ttdoc">Get Fault Mask (non-secure)</div></div>
<div class="ttc" id="agroup__compiler__conntrol__gr_html_ga3e40e4c553fc11588f7a4c2a19e789e0"><div class="ttname"><a href="group__compiler__conntrol__gr.html#ga3e40e4c553fc11588f7a4c2a19e789e0">__USED</a></div><div class="ttdeci">#define __USED</div><div class="ttdoc">Inform that a variable shall be retained in executable image.</div><div class="ttdef"><b>Definition:</b> Ref_CompilerControl.txt:218</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gga666eb0caeb12ec0e281415592ae89083a853e0f318108110e0527f29733d11f86"><div class="ttname"><a href="group__NVIC__gr.html#gga666eb0caeb12ec0e281415592ae89083a853e0f318108110e0527f29733d11f86">PVD_STM_IRQn</a></div><div class="ttdeci">@ PVD_STM_IRQn</div><div class="ttdoc">Device Interrupt 1: PVD through EXTI Line detection Interrupt.</div><div class="ttdef"><b>Definition:</b> Ref_NVIC.txt:401</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga9736fe816aec74fe886e7fb949734eab"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga9736fe816aec74fe886e7fb949734eab">__UQSUB8</a></div><div class="ttdeci">uint32_t __UQSUB8(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Quad 8-bit unsigned saturating subtraction.</div></div>
<div class="ttc" id="astructTPI__Type_html_ad98855854a719bbea33061e71529a472"><div class="ttname"><a href="structTPI__Type.html#ad98855854a719bbea33061e71529a472">TPI_Type::DEVTYPE</a></div><div class="ttdeci">__IM uint32_t DEVTYPE</div><div class="ttdoc">Offset: 0xFCC (R/ ) TPIU_DEVTYPE.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:301</div></div>
<div class="ttc" id="astructMPU__Type_html_a990c609b26d990b8ba832b110adfd353"><div class="ttname"><a href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">MPU_Type::RBAR</a></div><div class="ttdeci">__IOM uint32_t RBAR</div><div class="ttdoc">Offset: 0x00C (R/W) MPU Region Base Address Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:205</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gaf4350af7f2030c36f43b2c104a9d16cd"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gaf4350af7f2030c36f43b2c104a9d16cd">__SMLSD</a></div><div class="ttdeci">uint32_t __SMLSD(uint32_t val1, uint32_t val2, uint32_t val3)</div><div class="ttdoc">Q setting dual 16-bit signed multiply subtract with 32-bit accumulate.</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gga666eb0caeb12ec0e281415592ae89083a9cda5594d898247bfa9d16ad966724da"><div class="ttname"><a href="group__NVIC__gr.html#gga666eb0caeb12ec0e281415592ae89083a9cda5594d898247bfa9d16ad966724da">SecureFault_IRQn</a></div><div class="ttdeci">@ SecureFault_IRQn</div><div class="ttdoc">Exception 7: Secure Fault Interrupt [only on Armv8-M].</div><div class="ttdef"><b>Definition:</b> Ref_NVIC.txt:393</div></div>
<div class="ttc" id="astructDWT__Type_html_a2a509d8505c37a3b64f6b24993df5f3f"><div class="ttname"><a href="structDWT__Type.html#a2a509d8505c37a3b64f6b24993df5f3f">DWT_Type::MASK3</a></div><div class="ttdeci">__IOM uint32_t MASK3</div><div class="ttdoc">Offset: 0x054 (R/W) Mask Register 3.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:268</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_ga44b31316872e91bda1af7e17173de24b"><div class="ttname"><a href="group__NVIC__gr.html#ga44b31316872e91bda1af7e17173de24b">NVIC_ClearTargetState</a></div><div class="ttdeci">uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)</div><div class="ttdoc">Clear Interrupt Target State.</div></div>
<div class="ttc" id="aunionCONTROL__Type_html_a8cc085fea1c50a8bd9adea63931ee8e2"><div class="ttname"><a href="unionCONTROL__Type.html#a8cc085fea1c50a8bd9adea63931ee8e2">CONTROL_Type::SPSEL</a></div><div class="ttdeci">uint32_t SPSEL</div><div class="ttdoc">bit: 1 Stack to be used</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:74</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gad25ce96db0f17096bbd815f4817faf09"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gad25ce96db0f17096bbd815f4817faf09">__UXTAB16</a></div><div class="ttdeci">uint32_t __UXTAB16(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Extracted 16-bit to 32-bit unsigned addition.</div></div>
<div class="ttc" id="astructITM__Type_html_a962a970dfd286cad7f8a8577e87d4ad3"><div class="ttname"><a href="structITM__Type.html#a962a970dfd286cad7f8a8577e87d4ad3">ITM_Type::u16</a></div><div class="ttdeci">__OM uint16_t u16</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:163</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8"><div class="ttname"><a href="group__Core__Register__gr.html#ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8">__get_IPSR</a></div><div class="ttdeci">uint32_t __get_IPSR(void)</div><div class="ttdoc">Read the IPSR register.</div></div>
<div class="ttc" id="agroup__sau__trustzone__functions_html_ga6093bc5939ea8924fbcfdffb8f0553f1"><div class="ttname"><a href="group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1">TZ_SAU_Setup</a></div><div class="ttdeci">void TZ_SAU_Setup(void)</div><div class="ttdoc">Setup Secure Attribute Unit (SAU) and non-secure interrupts.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga4262f73be75efbac6b46ab7c71aa6cbc"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga4262f73be75efbac6b46ab7c71aa6cbc">__SSUB16</a></div><div class="ttdeci">uint32_t __SSUB16(uint32_t val1, uint32_t val2)</div><div class="ttdoc">GE setting dual 16-bit signed subtraction.</div></div>
<div class="ttc" id="agroup__nvic__trustzone__functions_html_gade6a8784339946fdd50575d7e65a3268"><div class="ttname"><a href="group__nvic__trustzone__functions.html#gade6a8784339946fdd50575d7e65a3268">TZ_NVIC_GetPriority_NS</a></div><div class="ttdeci">uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)</div><div class="ttdoc">Get Interrupt Priority (non-secure)</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_ga5866c75d6deb9148a1e9af6337eec50a"><div class="ttname"><a href="group__mpu8__functions.html#ga5866c75d6deb9148a1e9af6337eec50a">ARM_MPU_Enable_NS</a></div><div class="ttdeci">__STATIC_INLINE ARM_MPU_Enable_NS(uint32_t MPU_Control)</div></div>
<div class="ttc" id="agroup__context__trustzone__functions_html_gac106570f4905f82922fd335aeb08a1bf"><div class="ttname"><a href="group__context__trustzone__functions.html#gac106570f4905f82922fd335aeb08a1bf">TZ_StoreContext_S</a></div><div class="ttdeci">uint32_t TZ_StoreContext_S(TZ_MemoryId_t id)</div><div class="ttdoc">Store secure context (called on RTOS thread context switch)</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_ga62b37611e1ccbac47d747c98ef302746"><div class="ttname"><a href="group__NVIC__gr.html#ga62b37611e1ccbac47d747c98ef302746">NVIC_GetTargetState</a></div><div class="ttdeci">uint32_t NVIC_GetTargetState(IRQn_Type IRQn)</div><div class="ttdoc">Get Interrupt Target State.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga3a14e5485e59bf0f23595b7c2a94eb0b"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga3a14e5485e59bf0f23595b7c2a94eb0b">__UHADD8</a></div><div class="ttdeci">uint32_t __UHADD8(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Quad 8-bit unsigned addition with halved results.</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga513beada40cdd7123281f22482603bcc"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga513beada40cdd7123281f22482603bcc">__LDAEXB</a></div><div class="ttdeci">uint8_t __LDAEXB(volatile uint32_t *ptr)</div><div class="ttdoc">Load-Acquire Exclusive (8 bit)</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_gac526bc5bfcf048ce57a44c0c0cdadbe4"><div class="ttname"><a href="group__mpu8__functions.html#gac526bc5bfcf048ce57a44c0c0cdadbe4">ARM_MPU_ClrRegion_NS</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_ga3d0f688198289f72264f73cf72a742e8"><div class="ttname"><a href="group__mpu8__functions.html#ga3d0f688198289f72264f73cf72a742e8">ARM_MPU_SH_NON</a></div><div class="ttdeci">#define ARM_MPU_SH_NON</div><div class="ttdoc">Normal memory non-shareable</div><div class="ttdef"><b>Definition:</b> Ref_MPU8.txt:68</div></div>
<div class="ttc" id="astructDWT__Type_html_a9fe20c16c5167ca61486caf6832686d1"><div class="ttname"><a href="structDWT__Type.html#a9fe20c16c5167ca61486caf6832686d1">DWT_Type::EXCCNT</a></div><div class="ttdeci">__IOM uint32_t EXCCNT</div><div class="ttdoc">Offset: 0x00C (R/W) Exception Overhead Count Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:250</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gaa81b19849367d3cdb95ac108c500fa78"><div class="ttname"><a href="group__NVIC__gr.html#gaa81b19849367d3cdb95ac108c500fa78">NVIC_GetPriorityGrouping</a></div><div class="ttdeci">uint32_t NVIC_GetPriorityGrouping(void)</div><div class="ttdoc">Read the priority grouping [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="agroup__compiler__conntrol__gr_html_gaba87361bfad2ae52cfe2f40c1a1dbf9c"><div class="ttname"><a href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a></div><div class="ttdeci">#define __STATIC_INLINE</div><div class="ttdoc">Define a static function that may be inlined by the compiler.</div><div class="ttdef"><b>Definition:</b> Ref_CompilerControl.txt:130</div></div>
<div class="ttc" id="aunionxPSR__Type_html_af14df16ea0690070c45b95f2116b7a0a"><div class="ttname"><a href="unionxPSR__Type.html#af14df16ea0690070c45b95f2116b7a0a">xPSR_Type::V</a></div><div class="ttdeci">uint32_t V</div><div class="ttdoc">bit: 28 Overflow condition code flag</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:57</div></div>
<div class="ttc" id="agroup__nvic__trustzone__functions_html_gabc58593dea7803c1f1e1ed3b098f497c"><div class="ttname"><a href="group__nvic__trustzone__functions.html#gabc58593dea7803c1f1e1ed3b098f497c">TZ_NVIC_DisableIRQ_NS</a></div><div class="ttdeci">void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)</div><div class="ttdoc">Disable External Interrupt (non-secure)</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_gaa5587cc09031053a40a35c14ec36078a"><div class="ttname"><a href="group__Core__Register__gr.html#gaa5587cc09031053a40a35c14ec36078a">__set_FAULTMASK</a></div><div class="ttdeci">void __set_FAULTMASK(uint32_t faultMask)</div><div class="ttdoc">Set the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gaee6390f86965cb662500f690b0012092"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gaee6390f86965cb662500f690b0012092">__SMUADX</a></div><div class="ttdeci">uint32_t __SMUADX(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Q setting sum of dual 16-bit signed multiply with exchange.</div></div>
<div class="ttc" id="astructTPI__Type_html_ad6901bfd8a0089ca7e8a20475cf494a8"><div class="ttname"><a href="structTPI__Type.html#ad6901bfd8a0089ca7e8a20475cf494a8">TPI_Type::FSCR</a></div><div class="ttdeci">__IM uint32_t FSCR</div><div class="ttdoc">Offset: 0x308 (R/ ) Formatter Synchronization Counter Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:287</div></div>
<div class="ttc" id="agroup__ITM__Debug__gr_html_ga7f9bbabd9756d1a7eafb2d9bf27e0535"><div class="ttname"><a href="group__ITM__Debug__gr.html#ga7f9bbabd9756d1a7eafb2d9bf27e0535">ITM_CheckChar</a></div><div class="ttdeci">int32_t ITM_CheckChar(void)</div><div class="ttdoc">ITM Check Character.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gaf5448e591fe49161b6759b48aecb08fe"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gaf5448e591fe49161b6759b48aecb08fe">__SEL</a></div><div class="ttdeci">uint32_t __SEL(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Select bytes based on GE bits.</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga76bbe4374a5912362866cdc1ded4064a"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga76bbe4374a5912362866cdc1ded4064a">__USAT</a></div><div class="ttdeci">uint32_t __USAT(uint32_t value, uint32_t sat)</div><div class="ttdoc">Unsigned Saturate [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga38dce3dd13ba212e80ec3cff4abeb11a"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga38dce3dd13ba212e80ec3cff4abeb11a">__SXTB16</a></div><div class="ttdeci">uint32_t __SXTB16(uint32_t val)</div><div class="ttdoc">Dual extract 8-bits and sign extend each to 16-bits.</div></div>
<div class="ttc" id="astructSCB__Type_html"><div class="ttname"><a href="structSCB__Type.html">SCB_Type</a></div><div class="ttdoc">Structure type to access the System Control Block (SCB).</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:106</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gadc48b4ed09386aab48fa6b9c96d9034c"><div class="ttname"><a href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a></div><div class="ttdeci">#define CMSIS_NVIC_VIRTUAL</div><div class="ttdoc">Virtualization of the NVIC API.</div></div>
<div class="ttc" id="astructTPI__Type_html_a0e10e292cb019a832b03ddd055b2f6ac"><div class="ttname"><a href="structTPI__Type.html#a0e10e292cb019a832b03ddd055b2f6ac">TPI_Type::CLAIMCLR</a></div><div class="ttdeci">__IOM uint32_t CLAIMCLR</div><div class="ttdoc">Offset: 0xFA4 (R/W) Claim tag clear.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:298</div></div>
<div class="ttc" id="astructDWT__Type_html_a102eaa529d9098242851cb57c52b42d9"><div class="ttname"><a href="structDWT__Type.html#a102eaa529d9098242851cb57c52b42d9">DWT_Type::CYCCNT</a></div><div class="ttdeci">__IOM uint32_t CYCCNT</div><div class="ttdoc">Offset: 0x004 (R/W) Cycle Count Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:248</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gad1adad1b3f2667328cc0db6c6b4f41cf"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gad1adad1b3f2667328cc0db6c6b4f41cf">__SMLALDX</a></div><div class="ttdeci">unsigned long long __SMLALDX(uint32_t val1, uint32_t val2, unsigned long long val3)</div><div class="ttdoc">Dual 16-bit signed multiply with exchange with single 64-bit accumulator.</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga0bf9564ebc1613a8faba014275dac2a4"><div class="ttname"><a href="group__Core__Register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4">__set_MSP</a></div><div class="ttdeci">void __set_MSP(uint32_t topOfMainStack)</div><div class="ttdoc">Set the MSP register.</div></div>
<div class="ttc" id="astructFPU__Type_html_a4f19014defe6033d070b80af19ef627c"><div class="ttname"><a href="structFPU__Type.html#a4f19014defe6033d070b80af19ef627c">FPU_Type::MVFR0</a></div><div class="ttdeci">__IM uint32_t MVFR0</div><div class="ttdoc">Offset: 0x010 (R/ ) Media and FP Feature Register 0.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:225</div></div>
<div class="ttc" id="agroup__coreregister__trustzone__functions_html_gada00853d3e49fa8d21f375c53d28fa51"><div class="ttname"><a href="group__coreregister__trustzone__functions.html#gada00853d3e49fa8d21f375c53d28fa51">__TZ_get_MSPLIM_NS</a></div><div class="ttdeci">uint32_t __TZ_get_MSPLIM_NS(void)</div><div class="ttdoc">Get Main Stack Pointer Limit (non-secure) Devices without Armv8-M Main Extensions (i....</div></div>
<div class="ttc" id="agroup__mpu__functions_html_gac1a949403bf84eecaf407003fb553ae7"><div class="ttname"><a href="group__mpu__functions.html#gac1a949403bf84eecaf407003fb553ae7">ARM_MPU_OrderedMemcpy</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)</div></div>
<div class="ttc" id="aunionAPSR__Type_html_a8004d224aacb78ca37774c35f9156e7e"><div class="ttname"><a href="unionAPSR__Type.html#a8004d224aacb78ca37774c35f9156e7e">APSR_Type::V</a></div><div class="ttdeci">uint32_t V</div><div class="ttdoc">bit: 28 Overflow condition code flag</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:16</div></div>
<div class="ttc" id="aunionxPSR__Type_html_a40213a6b5620410cac83b0d89564609d"><div class="ttname"><a href="unionxPSR__Type.html#a40213a6b5620410cac83b0d89564609d">xPSR_Type::C</a></div><div class="ttdeci">uint32_t C</div><div class="ttdoc">bit: 29 Carry condition code flag</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:58</div></div>
<div class="ttc" id="agroup__Dcache__functions__m7_html_ga6468170f90d270caab8116e7a4f0b5fe"><div class="ttname"><a href="group__Dcache__functions__m7.html#ga6468170f90d270caab8116e7a4f0b5fe">SCB_DisableDCache</a></div><div class="ttdeci">__STATIC_INLINE void SCB_DisableDCache(void)</div><div class="ttdoc">Disable D-Cache.</div></div>
<div class="ttc" id="aRef__Peripheral_8txt_html_a286e3b913dbd236c7f48ea70c8821f4e"><div class="ttname"><a href="Ref__Peripheral_8txt.html#a286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a></div><div class="ttdeci">#define _VAL2FLD(field, value)</div><div class="ttdoc">Mask and shift a bit field value for assigning the result to a peripheral register.</div><div class="ttdef"><b>Definition:</b> Ref_Peripheral.txt:209</div></div>
<div class="ttc" id="aunionxPSR__Type_html_a2db9a52f6d42809627d1a7a607c5dbc5"><div class="ttname"><a href="unionxPSR__Type.html#a2db9a52f6d42809627d1a7a607c5dbc5">xPSR_Type::N</a></div><div class="ttdeci">uint32_t N</div><div class="ttdoc">bit: 31 Negative condition code flag</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:60</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_gaab6482d1f59f59e2b6b7efc1af391c99"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a></div><div class="ttdeci">uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)</div><div class="ttdoc">STR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="astructSCB__Type_html_a14ad254659362b9752c69afe3fd80934"><div class="ttname"><a href="structSCB__Type.html#a14ad254659362b9752c69afe3fd80934">SCB_Type::HFSR</a></div><div class="ttdeci">__IOM uint32_t HFSR</div><div class="ttdoc">Offset: 0x02C (R/W) HardFault Status Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:117</div></div>
<div class="ttc" id="astructSCB__Type_html_a3a4840c6fa4d1ee75544f4032c88ec34"><div class="ttname"><a href="structSCB__Type.html#a3a4840c6fa4d1ee75544f4032c88ec34">SCB_Type::SCR</a></div><div class="ttdeci">__IOM uint32_t SCR</div><div class="ttdoc">Offset: 0x010 (R/W) System Control Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:112</div></div>
<div class="ttc" id="astructITM__Type_html_ae773bf9f9dac64e6c28b14aa39f74275"><div class="ttname"><a href="structITM__Type.html#ae773bf9f9dac64e6c28b14aa39f74275">ITM_Type::u8</a></div><div class="ttdeci">__OM uint8_t u8</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:162</div></div>
<div class="ttc" id="astructFPU__Type_html_af1b708c5e413739150df3d16ca3b7061"><div class="ttname"><a href="structFPU__Type.html#af1b708c5e413739150df3d16ca3b7061">FPU_Type::FPCCR</a></div><div class="ttdeci">__IOM uint32_t FPCCR</div><div class="ttdoc">Offset: 0x004 (R/W) Floating-Point Context Control Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:222</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gga666eb0caeb12ec0e281415592ae89083a03c3cc89984928816d81793fc7bce4a2"><div class="ttname"><a href="group__NVIC__gr.html#gga666eb0caeb12ec0e281415592ae89083a03c3cc89984928816d81793fc7bce4a2">PendSV_IRQn</a></div><div class="ttdeci">@ PendSV_IRQn</div><div class="ttdoc">Exception 14: Pend SV Interrupt [not on Cortex-M0 variants].</div><div class="ttdef"><b>Definition:</b> Ref_NVIC.txt:397</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gae326e368a1624d2dfb4b97c626939257"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gae326e368a1624d2dfb4b97c626939257">__SMUAD</a></div><div class="ttdeci">uint32_t __SMUAD(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Q setting sum of dual 16-bit signed multiply.</div></div>
<div class="ttc" id="agroup__compiler__conntrol__gr_html_gab94ebeb20055f1848d7b707d3c7cfc5d"><div class="ttname"><a href="group__compiler__conntrol__gr.html#gab94ebeb20055f1848d7b707d3c7cfc5d">__VECTOR_TABLE</a></div><div class="ttdeci">#define __VECTOR_TABLE</div><div class="ttdoc">Symbol name used for the (static) interrupt vector table.</div><div class="ttdef"><b>Definition:</b> Ref_CompilerControl.txt:495</div></div>
<div class="ttc" id="astructDWT__Type_html"><div class="ttname"><a href="structDWT__Type.html">DWT_Type</a></div><div class="ttdoc">Structure type to access the Data Watchpoint and Trace Register (DWT).</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:245</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_ga61814eba4652a0fdfb76bbe222086327"><div class="ttname"><a href="group__mpu8__functions.html#ga61814eba4652a0fdfb76bbe222086327">ARM_MPU_Disable</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_Disable(void)</div></div>
<div class="ttc" id="astructSCB__Type_html_ad3e5b8934c647eb1b7383c1894f01380"><div class="ttname"><a href="structSCB__Type.html#ad3e5b8934c647eb1b7383c1894f01380">SCB_Type::AIRCR</a></div><div class="ttdeci">__IOM uint32_t AIRCR</div><div class="ttdoc">Offset: 0x00C (R/W) Application Interrupt and Reset Control Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:111</div></div>
<div class="ttc" id="astructDWT__Type_html_a85eb73d1848ac3f82d39d6c3e8910847"><div class="ttname"><a href="structDWT__Type.html#a85eb73d1848ac3f82d39d6c3e8910847">DWT_Type::COMP3</a></div><div class="ttdeci">__IOM uint32_t COMP3</div><div class="ttdoc">Offset: 0x050 (R/W) Comparator Register 3.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:267</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_ga7f8c6e09be98067d613e4df1832c543d"><div class="ttname"><a href="group__mpu8__functions.html#ga7f8c6e09be98067d613e4df1832c543d">ARM_MPU_Load_NS</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gaa1160f0cf76d6aa292fbad54a1aa6b74"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gaa1160f0cf76d6aa292fbad54a1aa6b74">__UADD16</a></div><div class="ttdeci">uint32_t __UADD16(uint32_t val1, uint32_t val2)</div><div class="ttdoc">GE setting dual 16-bit unsigned addition.</div></div>
<div class="ttc" id="agroup__system__init__gr_html_ga93f514700ccf00d08dbdcff7f1224eb2"><div class="ttname"><a href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a></div><div class="ttdeci">void SystemInit(void)</div><div class="ttdoc">Function to Initialize the system.</div></div>
<div class="ttc" id="agroup__coreregister__trustzone__functions_html_ga27bf1f88e794c30808ee73a29d46e358"><div class="ttname"><a href="group__coreregister__trustzone__functions.html#ga27bf1f88e794c30808ee73a29d46e358">__TZ_get_CONTROL_NS</a></div><div class="ttdeci">uint32_t __TZ_get_CONTROL_NS(void)</div><div class="ttdoc">Get Control register (non-secure)</div></div>
<div class="ttc" id="agroup__mpu__functions_html_gafa27b26d5847fa8e465584e376b6078a"><div class="ttname"><a href="group__mpu__functions.html#gafa27b26d5847fa8e465584e376b6078a">ARM_MPU_Load</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_Load(MPU_Region_t const *table, uint32_t cnt)</div></div>
<div class="ttc" id="astructDWT__Type_html_a821eb5e71f340ec077efc064cfc567db"><div class="ttname"><a href="structDWT__Type.html#a821eb5e71f340ec077efc064cfc567db">DWT_Type::MASK0</a></div><div class="ttdeci">__IOM uint32_t MASK0</div><div class="ttdoc">Offset: 0x024 (R/W) Mask Register 0.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:256</div></div>
<div class="ttc" id="astructITM__Type_html_ae2ce4d3a54df2fd11a197ccac4406cd0"><div class="ttname"><a href="structITM__Type.html#ae2ce4d3a54df2fd11a197ccac4406cd0">ITM_Type::IMCR</a></div><div class="ttdeci">__IOM uint32_t IMCR</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:175</div></div>
<div class="ttc" id="astructCoreDebug__Type_html_aeb3126abc4c258a858f21f356c0df6ee"><div class="ttname"><a href="structCoreDebug__Type.html#aeb3126abc4c258a858f21f356c0df6ee">CoreDebug_Type::DEMCR</a></div><div class="ttdeci">__IOM uint32_t DEMCR</div><div class="ttdoc">Offset: 0x00C (R/W) Debug Exception and Monitor Control Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:238</div></div>
<div class="ttc" id="agroup__Dcache__functions__m7_html_gace2d30db08887d0bdb818b8a785a5ce6"><div class="ttname"><a href="group__Dcache__functions__m7.html#gace2d30db08887d0bdb818b8a785a5ce6">SCB_InvalidateDCache</a></div><div class="ttdeci">__STATIC_INLINE void SCB_InvalidateDCache(void)</div><div class="ttdoc">Invalidate D-Cache.</div></div>
<div class="ttc" id="astructTPI__Type_html_aaa4c823c10f115f7517c82ef86a5a68d"><div class="ttname"><a href="structTPI__Type.html#aaa4c823c10f115f7517c82ef86a5a68d">TPI_Type::ITCTRL</a></div><div class="ttdeci">__IOM uint32_t ITCTRL</div><div class="ttdoc">Offset: 0xF00 (R/W) Integration Mode Control.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:295</div></div>
<div class="ttc" id="agroup__coreregister__trustzone__functions_html_ga6686c2ab5756b5049fad1644e89b3340"><div class="ttname"><a href="group__coreregister__trustzone__functions.html#ga6686c2ab5756b5049fad1644e89b3340">__TZ_set_PRIMASK_NS</a></div><div class="ttdeci">void __TZ_set_PRIMASK_NS(uint32_t priMask)</div><div class="ttdoc">Set Priority Mask (non-secure)</div></div>
<div class="ttc" id="agroup__sau__trustzone__functions_html_ga42e201cea0a4b09f588a28b751f726fb"><div class="ttname"><a href="group__sau__trustzone__functions.html#ga42e201cea0a4b09f588a28b751f726fb">TZ_SAU_Disable</a></div><div class="ttdeci">void TZ_SAU_Disable(void)</div><div class="ttdoc">Disable Security Attribution Unit (SAU)</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gab18fb9f6c5f4c70fdd73047f0f7c8395"><div class="ttname"><a href="group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">NVIC_GetPriority</a></div><div class="ttdeci">uint32_t NVIC_GetPriority(IRQn_Type IRQn)</div><div class="ttdoc">Get the priority of an interrupt.</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gga666eb0caeb12ec0e281415592ae89083a8e033fcef7aed98a31c60a7de206722c"><div class="ttname"><a href="group__NVIC__gr.html#gga666eb0caeb12ec0e281415592ae89083a8e033fcef7aed98a31c60a7de206722c">DebugMonitor_IRQn</a></div><div class="ttdeci">@ DebugMonitor_IRQn</div><div class="ttdoc">Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants].</div><div class="ttdef"><b>Definition:</b> Ref_NVIC.txt:396</div></div>
<div class="ttc" id="aunionxPSR__Type_html_a3e9120dcf1a829fc8d2302b4d0673970"><div class="ttname"><a href="unionxPSR__Type.html#a3e9120dcf1a829fc8d2302b4d0673970">xPSR_Type::ISR</a></div><div class="ttdeci">uint32_t ISR</div><div class="ttdoc">bit: 0.. 8 Exception number</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:46</div></div>
<div class="ttc" id="agroup__nvic__trustzone__functions_html_ga0d3b5db0685bd95cc8bd2f7ad0891d39"><div class="ttname"><a href="group__nvic__trustzone__functions.html#ga0d3b5db0685bd95cc8bd2f7ad0891d39">TZ_NVIC_SetPriorityGrouping_NS</a></div><div class="ttdeci">void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)</div><div class="ttdoc">Set Priority Grouping (non-secure)</div></div>
<div class="ttc" id="aunionCONTROL__Type_html_ac62cfff08e6f055e0101785bad7094cd"><div class="ttname"><a href="unionCONTROL__Type.html#ac62cfff08e6f055e0101785bad7094cd">CONTROL_Type::FPCA</a></div><div class="ttdeci">uint32_t FPCA</div><div class="ttdoc">bit: 2 FP extension active flag</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:75</div></div>
<div class="ttc" id="agroup__nvic__trustzone__functions_html_ga1bffd79bd6365d83281883b6c4b0f218"><div class="ttname"><a href="group__nvic__trustzone__functions.html#ga1bffd79bd6365d83281883b6c4b0f218">TZ_NVIC_GetActive_NS</a></div><div class="ttdeci">uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)</div><div class="ttdoc">Get Active Interrupt (non-secure)</div></div>
<div class="ttc" id="agroup__fpu__functions_html_ga6bcad99ce80a0e7e4ddc6f2379081756"><div class="ttname"><a href="group__fpu__functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756">SCB_GetFPUType</a></div><div class="ttdeci">__STATIC_INLINE uint32_t SCB_GetFPUType(void)</div><div class="ttdoc">Get the FPU type.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga753493a65493880c28baa82c151a0d61"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga753493a65493880c28baa82c151a0d61">__QSUB8</a></div><div class="ttdeci">uint32_t __QSUB8(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Q setting quad 8-bit saturating subtract.</div></div>
<div class="ttc" id="astructITM__Type_html_a89ea1d805a668d6589b22d8e678eb6a4"><div class="ttname"><a href="structITM__Type.html#a89ea1d805a668d6589b22d8e678eb6a4">ITM_Type::PID1</a></div><div class="ttdeci">__IM uint32_t PID1</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:187</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga625bc4ac0b1d50de9bcd13d9f050030e"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga625bc4ac0b1d50de9bcd13d9f050030e">__STRT</a></div><div class="ttdeci">void __STRT(uint32_t value, uint32_t ptr)</div><div class="ttdoc">STRT Unprivileged (32 bit)</div></div>
<div class="ttc" id="astructITM__Type_html_a8471c4d77b7107cf580587509da69f38"><div class="ttname"><a href="structITM__Type.html#a8471c4d77b7107cf580587509da69f38">ITM_Type::PID2</a></div><div class="ttdeci">__IM uint32_t PID2</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:188</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gga666eb0caeb12ec0e281415592ae89083a6895237c9443601ac832efa635dd8bbf"><div class="ttname"><a href="group__NVIC__gr.html#gga666eb0caeb12ec0e281415592ae89083a6895237c9443601ac832efa635dd8bbf">UsageFault_IRQn</a></div><div class="ttdeci">@ UsageFault_IRQn</div><div class="ttdoc">Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants].</div><div class="ttdef"><b>Definition:</b> Ref_NVIC.txt:391</div></div>
<div class="ttc" id="agroup__Icache__functions__m7_html_gaba757390852f95b3ac2d8638c717d8d8"><div class="ttname"><a href="group__Icache__functions__m7.html#gaba757390852f95b3ac2d8638c717d8d8">SCB_DisableICache</a></div><div class="ttdeci">__STATIC_INLINE void SCB_DisableICache(void)</div><div class="ttdoc">Disable I-Cache.</div></div>
<div class="ttc" id="astructTPI__Type_html_a9e5e4421ef9c3d5b7ff8b24abd4e99b3"><div class="ttname"><a href="structTPI__Type.html#a9e5e4421ef9c3d5b7ff8b24abd4e99b3">TPI_Type::ACPR</a></div><div class="ttdeci">__IOM uint32_t ACPR</div><div class="ttdoc">Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:281</div></div>
<div class="ttc" id="astructFPU__Type_html_a55263b468d0f8e11ac77aec9ff87c820"><div class="ttname"><a href="structFPU__Type.html#a55263b468d0f8e11ac77aec9ff87c820">FPU_Type::FPCAR</a></div><div class="ttdeci">__IOM uint32_t FPCAR</div><div class="ttdoc">Offset: 0x008 (R/W) Floating-Point Context Address Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:223</div></div>
<div class="ttc" id="astructARM__MPU__Region__t_html_a6a3e404b403c8df611f27d902d745d8d"><div class="ttname"><a href="structARM__MPU__Region__t.html#a6a3e404b403c8df611f27d902d745d8d">ARM_MPU_Region_t::RASR</a></div><div class="ttdeci">uint32_t RASR</div><div class="ttdoc">The region attribute and size register value (RASR), see ARM_MPU_RASR.</div><div class="ttdef"><b>Definition:</b> Ref_MPU.txt:86</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga87618799672e1511e33964bc71467eb3"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga87618799672e1511e33964bc71467eb3">__QASX</a></div><div class="ttdeci">uint32_t __QASX(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Q setting dual 16-bit add and subtract with exchange.</div></div>
<div class="ttc" id="astructTPI__Type_html_a6c47a0b4c7ffc66093ef993d36bb441c"><div class="ttname"><a href="structTPI__Type.html#a6c47a0b4c7ffc66093ef993d36bb441c">TPI_Type::FFSR</a></div><div class="ttdeci">__IM uint32_t FFSR</div><div class="ttdoc">Offset: 0x300 (R/ ) Formatter and Flush Status Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:285</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga5ec4e2e231d15e5c692233feb3806187"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga5ec4e2e231d15e5c692233feb3806187">__UQSUB16</a></div><div class="ttdeci">uint32_t __UQSUB16(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Dual 16-bit unsigned saturating subtraction.</div></div>
<div class="ttc" id="agroup__compiler__conntrol__gr_html_ga1002e751427b1189f92787d4e4eef965"><div class="ttname"><a href="group__compiler__conntrol__gr.html#ga1002e751427b1189f92787d4e4eef965">__INITIAL_SP</a></div><div class="ttdeci">#define __INITIAL_SP</div><div class="ttdoc">Compiler/linker symbol specifiying the location of the main stack (MSP).</div><div class="ttdef"><b>Definition:</b> Ref_CompilerControl.txt:459</div></div>
<div class="ttc" id="astructDWT__Type_html_a579ae082f58a0317b7ef029b20f52889"><div class="ttname"><a href="structDWT__Type.html#a579ae082f58a0317b7ef029b20f52889">DWT_Type::FUNCTION0</a></div><div class="ttdeci">__IOM uint32_t FUNCTION0</div><div class="ttdoc">Offset: 0x028 (R/W) Function Register 0.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:257</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_gace025d3a1f85d2ab9bae7288838d6bc8"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#gace025d3a1f85d2ab9bae7288838d6bc8">__STLB</a></div><div class="ttdeci">void __STLB(uint8_t value, volatile uint8_t *ptr)</div><div class="ttdoc">Store-Release (8 bit)</div></div>
<div class="ttc" id="astructSCB__Type_html_a3f8e7e58be4e41c88dfa78f54589271c"><div class="ttname"><a href="structSCB__Type.html#a3f8e7e58be4e41c88dfa78f54589271c">SCB_Type::BFAR</a></div><div class="ttdeci">__IOM uint32_t BFAR</div><div class="ttdoc">Offset: 0x038 (R/W) BusFault Address Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:120</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_gacb2a8ca6eae1ba4b31161578b720c199"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">__DSB</a></div><div class="ttdeci">void __DSB(void)</div><div class="ttdoc">Data Synchronization Barrier.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga48a55df1c3e73923b73819d7c19b392d"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga48a55df1c3e73923b73819d7c19b392d">__UHSUB8</a></div><div class="ttdeci">uint32_t __UHSUB8(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Quad 8-bit unsigned subtraction with halved results.</div></div>
<div class="ttc" id="astructITM__Type_html_a30bb2b166b1723867da4a708935677ba"><div class="ttname"><a href="structITM__Type.html#a30bb2b166b1723867da4a708935677ba">ITM_Type::CID0</a></div><div class="ttdeci">__IM uint32_t CID0</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:190</div></div>
<div class="ttc" id="astructDWT__Type_html_a416a54e2084ce66e5ca74f152a5ecc70"><div class="ttname"><a href="structDWT__Type.html#a416a54e2084ce66e5ca74f152a5ecc70">DWT_Type::SLEEPCNT</a></div><div class="ttdeci">__IOM uint32_t SLEEPCNT</div><div class="ttdoc">Offset: 0x010 (R/W) Sleep Count Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:251</div></div>
<div class="ttc" id="astructSCB__Type_html_a85dd6fe77aab17e7ea89a52c59da6004"><div class="ttname"><a href="structSCB__Type.html#a85dd6fe77aab17e7ea89a52c59da6004">SCB_Type::DFR</a></div><div class="ttdeci">__IM uint32_t DFR</div><div class="ttdoc">Offset: 0x048 (R/ ) Debug Feature Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:123</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gafa9af218db3934a692fb06fa728d8031"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gafa9af218db3934a692fb06fa728d8031">__UQADD8</a></div><div class="ttdeci">uint32_t __UQADD8(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Quad 8-bit unsigned saturating addition.</div></div>
<div class="ttc" id="agroup__Dcache__functions__m7_html_ga63aa640d9006021a796a5dcf9c7180b6"><div class="ttname"><a href="group__Dcache__functions__m7.html#ga63aa640d9006021a796a5dcf9c7180b6">SCB_EnableDCache</a></div><div class="ttdeci">__STATIC_INLINE void SCB_EnableDCache(void)</div><div class="ttdoc">Enable D-Cache.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gab3d7fd00d113b20fb3741a17394da762"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gab3d7fd00d113b20fb3741a17394da762">__UADD8</a></div><div class="ttdeci">uint32_t __UADD8(uint32_t val1, uint32_t val2)</div><div class="ttdoc">GE setting quad 8-bit unsigned addition.</div></div>
<div class="ttc" id="agroup__context__trustzone__functions_html_ga4748f6bcdd5fed279ac5a6cd7eca2689"><div class="ttname"><a href="group__context__trustzone__functions.html#ga4748f6bcdd5fed279ac5a6cd7eca2689">TZ_LoadContext_S</a></div><div class="ttdeci">uint32_t TZ_LoadContext_S(TZ_MemoryId_t id)</div><div class="ttdoc">Load secure context (called on RTOS thread context switch)</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gadecfdfabc328d8939d49d996f2fd4482"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gadecfdfabc328d8939d49d996f2fd4482">__UQSAX</a></div><div class="ttdeci">uint32_t __UQSAX(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Dual 16-bit unsigned saturating subtraction and addition with exchange.</div></div>
<div class="ttc" id="astructSCnSCB__Type_html_a13af9b718dde7481f1c0344f00593c23"><div class="ttname"><a href="structSCnSCB__Type.html#a13af9b718dde7481f1c0344f00593c23">SCnSCB_Type::ACTLR</a></div><div class="ttdeci">__IOM uint32_t ACTLR</div><div class="ttdoc">Offset: 0x008 (R/W) Auxiliary Control Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:139</div></div>
<div class="ttc" id="aunionxPSR__Type_html_af438e0f407357e914a70b5bd4d6a97c5"><div class="ttname"><a href="unionxPSR__Type.html#af438e0f407357e914a70b5bd4d6a97c5">xPSR_Type::_reserved0</a></div><div class="ttdeci">uint32_t _reserved0</div><div class="ttdoc">bit: 9..23 Reserved</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:48</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_gad3efec76c3bfa2b8528ded530386c563"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#gad3efec76c3bfa2b8528ded530386c563">__WFE</a></div><div class="ttdeci">void __WFE(void)</div><div class="ttdoc">Wait For Event.</div></div>
<div class="ttc" id="aunionCONTROL__Type_html"><div class="ttname"><a href="unionCONTROL__Type.html">CONTROL_Type</a></div><div class="ttdoc">Union type to access the Control Registers (CONTROL).</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:69</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_ga95a8329a680b051ecf3ee8f516acc662"><div class="ttname"><a href="group__NVIC__gr.html#ga95a8329a680b051ecf3ee8f516acc662">NVIC_GetPendingIRQ</a></div><div class="ttdeci">uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Get the pending device specific interrupt.</div></div>
<div class="ttc" id="astructITM__Type_html_a8000b92e4e528ae7ac4cb8b8d9f6757d"><div class="ttname"><a href="structITM__Type.html#a8000b92e4e528ae7ac4cb8b8d9f6757d">ITM_Type::CID2</a></div><div class="ttdeci">__IM uint32_t CID2</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:192</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_gaa762b8bc5634ce38cb14d62a6b2aee32"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#gaa762b8bc5634ce38cb14d62a6b2aee32">__LDRHT</a></div><div class="ttdeci">uint16_t __LDRHT(uint16_t ptr)</div><div class="ttdoc">LDRT Unprivileged (16 bit)</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga047c3bebca3d0ae348ab8370a046301d"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga047c3bebca3d0ae348ab8370a046301d">__STLEXH</a></div><div class="ttdeci">uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)</div><div class="ttdoc">Store-Release Exclusive (16 bit)</div></div>
<div class="ttc" id="agroup__ITM__Debug__gr_html_gaaa7c716331f74d644bf6bf25cd3392d1"><div class="ttname"><a href="group__ITM__Debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a></div><div class="ttdeci">uint32_t ITM_SendChar(uint32_t ch)</div><div class="ttdoc">Transmits a character via channel 0.</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_gad6d7eca9ddd1d9072dd7b020cfe64905"><div class="ttname"><a href="group__Core__Register__gr.html#gad6d7eca9ddd1d9072dd7b020cfe64905">__get_FPSCR</a></div><div class="ttdeci">uint32_t __get_FPSCR(void)</div><div class="ttdoc">Read the FPSCR register [only Cortex-M4 and Cortex-M7].</div></div>
<div class="ttc" id="astructFPU__Type_html_a58d1989664a06db6ec2e122eefa9f04a"><div class="ttname"><a href="structFPU__Type.html#a58d1989664a06db6ec2e122eefa9f04a">FPU_Type::FPDSCR</a></div><div class="ttdeci">__IOM uint32_t FPDSCR</div><div class="ttdoc">Offset: 0x00C (R/W) Floating-Point Default Status Control Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:224</div></div>
<div class="ttc" id="astructSCB__Type_html_a21e08d546d8b641bee298a459ea73e46"><div class="ttname"><a href="structSCB__Type.html#a21e08d546d8b641bee298a459ea73e46">SCB_Type::CPUID</a></div><div class="ttdeci">__IM uint32_t CPUID</div><div class="ttdoc">Offset: 0x000 (R/ ) CPUID Base Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:108</div></div>
<div class="ttc" id="agroup__mpu__functions_html_ga31406efd492ec9a091a70ffa2d8a42fb"><div class="ttname"><a href="group__mpu__functions.html#ga31406efd492ec9a091a70ffa2d8a42fb">ARM_MPU_Enable</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_CTRL)</div><div class="ttdoc">Enable the memory protection unit (MPU) and.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gabb5bcba694bf17b141c32e6a8474f60e"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gabb5bcba694bf17b141c32e6a8474f60e">__SMUSDX</a></div><div class="ttdeci">uint32_t __SMUSDX(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Dual 16-bit signed multiply with exchange returning difference.</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_ga530ad9fda2ed1c8b70e439ecfe80591f"><div class="ttname"><a href="group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ</a></div><div class="ttdeci">void NVIC_EnableIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Enable a device specific interrupt.</div></div>
<div class="ttc" id="agroup__coreregister__trustzone__functions_html_ga92c187f0b4d53627b59e0fd0bda0b0df"><div class="ttname"><a href="group__coreregister__trustzone__functions.html#ga92c187f0b4d53627b59e0fd0bda0b0df">__TZ_set_BASEPRI_NS</a></div><div class="ttdeci">void __TZ_set_BASEPRI_NS(uint32_t basePri)</div><div class="ttdoc">Set Base Priority (non-secure)</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gacb7257dc3b8e9acbd0ef0e31ff87d4b8"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gacb7257dc3b8e9acbd0ef0e31ff87d4b8">__USUB8</a></div><div class="ttdeci">uint32_t __USUB8(uint32_t val1, uint32_t val2)</div><div class="ttdoc">GE setting quad 8-bit unsigned subtract.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gac3ec7215b354d925a239f3b31df2b77b"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gac3ec7215b354d925a239f3b31df2b77b">__SHSUB8</a></div><div class="ttdeci">uint32_t __SHSUB8(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Quad 8-bit signed subtraction with halved results.</div></div>
<div class="ttc" id="astructDWT__Type_html_a00ac4d830dfe0070a656cda9baed170f"><div class="ttname"><a href="structDWT__Type.html#a00ac4d830dfe0070a656cda9baed170f">DWT_Type::MASK2</a></div><div class="ttdeci">__IOM uint32_t MASK2</div><div class="ttdoc">Offset: 0x044 (R/W) Mask Register 2.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:264</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_ga1b47d17e90b6a03e7bd1ec6a0d549b46"><div class="ttname"><a href="group__NVIC__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46">NVIC_SystemReset</a></div><div class="ttdeci">void NVIC_SystemReset(void)</div><div class="ttdoc">Reset the system.</div></div>
<div class="ttc" id="astructTPI__Type_html_a3f68b6e73561b4849ebf953a894df8d2"><div class="ttname"><a href="structTPI__Type.html#a3f68b6e73561b4849ebf953a894df8d2">TPI_Type::FFCR</a></div><div class="ttdeci">__IOM uint32_t FFCR</div><div class="ttdoc">Offset: 0x304 (R/W) Formatter and Flush Control Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:286</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga9e2cc5117e79578a08b25f1e89022966"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga9e2cc5117e79578a08b25f1e89022966">__UQADD16</a></div><div class="ttdeci">uint32_t __UQADD16(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Dual 16-bit unsigned saturating addition.</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga25691650de536f9b248b15f6dc4a3e70"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga25691650de536f9b248b15f6dc4a3e70">__STLH</a></div><div class="ttdeci">void __STLH(uint16_t value, volatile uint16_t *ptr)</div><div class="ttdoc">Store-Release (16 bit)</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_ga3b885147ef9965ecede49614de8df9d2"><div class="ttname"><a href="group__NVIC__gr.html#ga3b885147ef9965ecede49614de8df9d2">NVIC_SetPendingIRQ</a></div><div class="ttdeci">void NVIC_SetPendingIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Set a device specific interrupt to pending.</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga93c09b4709394d81977300d5f84950e5"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga93c09b4709394d81977300d5f84950e5">__ISB</a></div><div class="ttdeci">void __ISB(void)</div><div class="ttdoc">Instruction Synchronization Barrier.</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga211618c03a0bf3264a7b22ad626d4f0a"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga211618c03a0bf3264a7b22ad626d4f0a">__REVSH</a></div><div class="ttdeci">int16_t __REVSH(int16_t value)</div><div class="ttdoc">Reverse byte order (16 bit)</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_ga5bb7f43ad92937c039dee3d36c3c2798"><div class="ttname"><a href="group__NVIC__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798">NVIC_SetPriority</a></div><div class="ttdeci">void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)</div><div class="ttdoc">Set the priority for an interrupt.</div></div>
<div class="ttc" id="astructMPU__Type_html"><div class="ttname"><a href="structMPU__Type.html">MPU_Type</a></div><div class="ttdoc">Structure type to access the Memory Protection Unit (MPU).</div><div class="ttdef"><b>Definition:</b> Ref_MPU.txt:29</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga732e08184154f44a617963cc65ff95bd"><div class="ttname"><a href="group__Core__Register__gr.html#ga732e08184154f44a617963cc65ff95bd">__get_xPSR</a></div><div class="ttdeci">uint32_t __get_xPSR(void)</div><div class="ttdoc">Read the xPSR register.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gae0c86f3298532183f3a29f5bb454d354"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gae0c86f3298532183f3a29f5bb454d354">__SMLAD</a></div><div class="ttdeci">uint32_t __SMLAD(uint32_t val1, uint32_t val2, uint32_t val3)</div><div class="ttdoc">Q setting dual 16-bit signed multiply with single 32-bit accumulator.</div></div>
<div class="ttc" id="astructSCB__Type_html_ab65372404ce64b0f0b35e2709429404e"><div class="ttname"><a href="structSCB__Type.html#ab65372404ce64b0f0b35e2709429404e">SCB_Type::AFSR</a></div><div class="ttdeci">__IOM uint32_t AFSR</div><div class="ttdoc">Offset: 0x03C (R/W) Auxiliary Fault Status Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:121</div></div>
<div class="ttc" id="aunionAPSR__Type_html_afbce95646fd514c10aa85ec0a33db728"><div class="ttname"><a href="unionAPSR__Type.html#afbce95646fd514c10aa85ec0a33db728">APSR_Type::_reserved0</a></div><div class="ttdeci">uint32_t _reserved0</div><div class="ttdoc">bit: 0..26 Reserved</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:9</div></div>
<div class="ttc" id="agroup__coreregister__trustzone__functions_html_ga4f0912db7bc65439d23817c1d372a7a4"><div class="ttname"><a href="group__coreregister__trustzone__functions.html#ga4f0912db7bc65439d23817c1d372a7a4">__TZ_set_FAULTMASK_NS</a></div><div class="ttdeci">void __TZ_set_FAULTMASK_NS(uint32_t faultMask)</div><div class="ttdoc">Set Fault Mask (non-secure)</div></div>
<div class="ttc" id="astructMPU__Type_html_a80d534f0dfc080c841e1772c7a68e1a2"><div class="ttname"><a href="structMPU__Type.html#a80d534f0dfc080c841e1772c7a68e1a2">MPU_Type::RBAR_A2</a></div><div class="ttdeci">__IOM uint32_t RBAR_A2</div><div class="ttdoc">Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:209</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_ga736ba13a76eb37ef6e2c253be8b0331c"><div class="ttname"><a href="group__NVIC__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c">NVIC_DisableIRQ</a></div><div class="ttdeci">void NVIC_DisableIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Disable a device specific interrupt.</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_ga9dcb0afddf4ac351f33f3c7a5169c62c"><div class="ttname"><a href="group__mpu8__functions.html#ga9dcb0afddf4ac351f33f3c7a5169c62c">ARM_MPU_ClrRegion</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)</div></div>
<div class="ttc" id="agroup__Dcache__functions__m7_html_ga696fadbf7b9cc71dad42fab61873a40d"><div class="ttname"><a href="group__Dcache__functions__m7.html#ga696fadbf7b9cc71dad42fab61873a40d">SCB_CleanDCache_by_Addr</a></div><div class="ttdeci">__STATIC_INLINE void SCB_CleanDCache_by_Addr(uint32_t *addr, int32_t dsize)</div><div class="ttdoc">D-Cache Clean by address.</div></div>
<div class="ttc" id="aunionIPSR__Type_html_ad2eb0a06de4f03f58874a727716aa9aa"><div class="ttname"><a href="unionIPSR__Type.html#ad2eb0a06de4f03f58874a727716aa9aa">IPSR_Type::_reserved0</a></div><div class="ttdeci">uint32_t _reserved0</div><div class="ttdoc">bit: 9..31 Reserved</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:33</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga578a082747436772c482c96d7a58e45e"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga578a082747436772c482c96d7a58e45e">__USAX</a></div><div class="ttdeci">uint32_t __USAX(uint32_t val1, uint32_t val2)</div><div class="ttdoc">GE setting dual 16-bit unsigned subtract and add with exchange.</div></div>
<div class="ttc" id="astructITM__Type_html_a43451f43f514108d9eaed5b017f8d921"><div class="ttname"><a href="structITM__Type.html#a43451f43f514108d9eaed5b017f8d921">ITM_Type::CID3</a></div><div class="ttdeci">__IM uint32_t CID3</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:193</div></div>
<div class="ttc" id="agroup__context__trustzone__functions_html_ga926e2ec472535a6d2b8125be1a79e3c0"><div class="ttname"><a href="group__context__trustzone__functions.html#ga926e2ec472535a6d2b8125be1a79e3c0">TZ_InitContextSystem_S</a></div><div class="ttdeci">uint32_t TZ_InitContextSystem_S(void)</div><div class="ttdoc">Initialize secure context memory system.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gac8855c07044239ea775c8128013204f0"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gac8855c07044239ea775c8128013204f0">__USAD8</a></div><div class="ttdeci">uint32_t __USAD8(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Unsigned sum of quad 8-bit unsigned absolute difference.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga31328467f0f91b8ff9ae9a01682ad3bf"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga31328467f0f91b8ff9ae9a01682ad3bf">__SHSUB16</a></div><div class="ttdeci">uint32_t __SHSUB16(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Dual 16-bit signed subtraction with halved results.</div></div>
<div class="ttc" id="astructNVIC__Type_html_a37de89637466e007171c6b135299bc75"><div class="ttname"><a href="structNVIC__Type.html#a37de89637466e007171c6b135299bc75">NVIC_Type::STIR</a></div><div class="ttdeci">__OM uint32_t STIR</div><div class="ttdoc">Offset: 0xE00 ( /W) Software Trigger Interrupt Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:99</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga5eff3ae5eabcd73f3049996ca391becb"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga5eff3ae5eabcd73f3049996ca391becb">__UQASX</a></div><div class="ttdeci">uint32_t __UQASX(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Dual 16-bit unsigned saturating addition and subtraction with exchange.</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_ga5100a150a755902af2455a455a329ef9"><div class="ttname"><a href="group__mpu8__functions.html#ga5100a150a755902af2455a455a329ef9">ARM_MPU_SetMemAttr_NS</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)</div></div>
<div class="ttc" id="astructDWT__Type_html_acc05d89bdb1b4fe2fa499920ec02d0b1"><div class="ttname"><a href="structDWT__Type.html#acc05d89bdb1b4fe2fa499920ec02d0b1">DWT_Type::LSUCNT</a></div><div class="ttdeci">__IOM uint32_t LSUCNT</div><div class="ttdoc">Offset: 0x014 (R/W) LSU Count Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:252</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gad78f447e891789b4d8f2e5b21eeda354"><div class="ttname"><a href="group__NVIC__gr.html#gad78f447e891789b4d8f2e5b21eeda354">NVIC_SetPriorityGrouping</a></div><div class="ttdeci">void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)</div><div class="ttdoc">Set priority grouping [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="agroup__context__trustzone__functions_html_gac84f678fbe974f8b02c683e0b8046524"><div class="ttname"><a href="group__context__trustzone__functions.html#gac84f678fbe974f8b02c683e0b8046524">TZ_FreeModuleContext_S</a></div><div class="ttdeci">uint32_t TZ_FreeModuleContext_S(TZ_MemoryId_t id)</div><div class="ttdoc">Free context memory that was previously allocated with TZ_AllocModuleContext_S.</div></div>
<div class="ttc" id="astructARM__MPU__Region__t_html"><div class="ttname"><a href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a></div><div class="ttdoc">Setup information of a single MPU Region.</div><div class="ttdef"><b>Definition:</b> Ref_MPU.txt:84</div></div>
<div class="ttc" id="astructSCB__Type_html_a191579bde0d21ff51d30a714fd887033"><div class="ttname"><a href="structSCB__Type.html#a191579bde0d21ff51d30a714fd887033">SCB_Type::DFSR</a></div><div class="ttdeci">__IOM uint32_t DFSR</div><div class="ttdoc">Offset: 0x030 (R/W) Debug Fault Status Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:118</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_gaeaaa071276ba7956944e6c3dc05d677e"><div class="ttname"><a href="group__mpu8__functions.html#gaeaaa071276ba7956944e6c3dc05d677e">ARM_MPU_RLAR</a></div><div class="ttdeci">#define ARM_MPU_RLAR(LIMIT, IDX)</div><div class="ttdoc">Region Limit Address Register value.</div><div class="ttdef"><b>Definition:</b> Ref_MPU8.txt:99</div></div>
<div class="ttc" id="astructITM__Type_html_a3861c67933a24dd6632288c4ed0b80c8"><div class="ttname"><a href="structITM__Type.html#a3861c67933a24dd6632288c4ed0b80c8">ITM_Type::LSR</a></div><div class="ttdeci">__IM uint32_t LSR</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:178</div></div>
<div class="ttc" id="astructCoreDebug__Type_html"><div class="ttname"><a href="structCoreDebug__Type.html">CoreDebug_Type</a></div><div class="ttdoc">Structure type to access the Core Debug Register (CoreDebug).</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:233</div></div>
<div class="ttc" id="astructFPU__Type_html_a66f8cfa49a423b480001a4e101bf842d"><div class="ttname"><a href="structFPU__Type.html#a66f8cfa49a423b480001a4e101bf842d">FPU_Type::MVFR1</a></div><div class="ttdeci">__IM uint32_t MVFR1</div><div class="ttdoc">Offset: 0x014 (R/ ) Media and FP Feature Register 1.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:226</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga70b4e1a6c1c86eb913fb9d6e8400156f"><div class="ttname"><a href="group__Core__Register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f">__set_PRIMASK</a></div><div class="ttdeci">void __set_PRIMASK(uint32_t priMask)</div><div class="ttdoc">Set the Priority Mask bit.</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_ga0688c59605b119c53c71b2505ab23eb5"><div class="ttname"><a href="group__NVIC__gr.html#ga0688c59605b119c53c71b2505ab23eb5">NVIC_EncodePriority</a></div><div class="ttdeci">uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</div><div class="ttdoc">Encodes Priority [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_gab6094419f2abd678f1f3b121cd115049"><div class="ttname"><a href="group__mpu8__functions.html#gab6094419f2abd678f1f3b121cd115049">ARM_MPU_LoadEx</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type *mpu, uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)</div></div>
<div class="ttc" id="astructITM__Type_html_af317d5e2d946d70e6fb67c02b92cc8a3"><div class="ttname"><a href="structITM__Type.html#af317d5e2d946d70e6fb67c02b92cc8a3">ITM_Type::PID3</a></div><div class="ttdeci">__IM uint32_t PID3</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:189</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_ga1799413f08a157d636a1491371c15ce2"><div class="ttname"><a href="group__mpu8__functions.html#ga1799413f08a157d636a1491371c15ce2">ARM_MPU_SetMemAttrEx</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type *mpu, uint8_t idx, uint8_t attr)</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga914dfa8eff7ca53380dd54cf1d8bebd9"><div class="ttname"><a href="group__Core__Register__gr.html#ga914dfa8eff7ca53380dd54cf1d8bebd9">__get_PSP</a></div><div class="ttdeci">uint32_t __get_PSP(void)</div><div class="ttdoc">Read the PSP register.</div></div>
<div class="ttc" id="aunionAPSR__Type_html_ae4c2ef8c9430d7b7bef5cbfbbaed3a94"><div class="ttname"><a href="unionAPSR__Type.html#ae4c2ef8c9430d7b7bef5cbfbbaed3a94">APSR_Type::w</a></div><div class="ttdeci">uint32_t w</div><div class="ttdoc">Type used for word access.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:21</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_gae7f955b91595cfd82a03e4b437c59afe"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#gae7f955b91595cfd82a03e4b437c59afe">__STLEX</a></div><div class="ttdeci">uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)</div><div class="ttdoc">Store-Release Exclusive (32 bit)</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga028f0732b961fb6e5209326fb3855261"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga028f0732b961fb6e5209326fb3855261">__UHASX</a></div><div class="ttdeci">uint32_t __UHASX(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Dual 16-bit unsigned addition and subtraction with halved results and exchange.</div></div>
<div class="ttc" id="astructMPU__Type_html_a8f00c4a5e31b0a8d103ed3b0732c17a3"><div class="ttname"><a href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">MPU_Type::RASR</a></div><div class="ttdeci">__IOM uint32_t RASR</div><div class="ttdoc">Offset: 0x010 (R/W) MPU Region Attribute and Size Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:206</div></div>
<div class="ttc" id="astructTPI__Type_html_ab358319b969d3fed0f89bbe33e9f1652"><div class="ttname"><a href="structTPI__Type.html#ab358319b969d3fed0f89bbe33e9f1652">TPI_Type::ITATBCTR2</a></div><div class="ttdeci">__IM uint32_t ITATBCTR2</div><div class="ttdoc">Offset: 0xEF0 (R/ ) ITATBCTR2.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:291</div></div>
<div class="ttc" id="astructSysTick__Type_html_a9b5420d17e8e43104ddd4ae5a610af93"><div class="ttname"><a href="structSysTick__Type.html#a9b5420d17e8e43104ddd4ae5a610af93">SysTick_Type::VAL</a></div><div class="ttdeci">__IOM uint32_t VAL</div><div class="ttdoc">Offset: 0x008 (R/W) SysTick Current Value Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:150</div></div>
<div class="ttc" id="astructTPI__Type_html_a12f79d4e3ddc69893ba8bff890d04cc5"><div class="ttname"><a href="structTPI__Type.html#a12f79d4e3ddc69893ba8bff890d04cc5">TPI_Type::SPPR</a></div><div class="ttdeci">__IOM uint32_t SPPR</div><div class="ttdoc">Offset: 0x0F0 (R/W) Selected Pin Protocol Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:283</div></div>
<div class="ttc" id="agroup__compiler__conntrol__gr_html_ga4f65c96effa79fbd610fea43ee7d745b"><div class="ttname"><a href="group__compiler__conntrol__gr.html#ga4f65c96effa79fbd610fea43ee7d745b">__VECTOR_TABLE_ATTRIBUTE</a></div><div class="ttdeci">#define __VECTOR_TABLE_ATTRIBUTE</div><div class="ttdoc">Additional decl specs to be used when defining the (static) interrupt vector table.</div><div class="ttdef"><b>Definition:</b> Ref_CompilerControl.txt:508</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga9464d75db32846aa8295c3c3adfacb41"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga9464d75db32846aa8295c3c3adfacb41">__LDRBT</a></div><div class="ttdeci">uint8_t __LDRBT(uint8_t ptr)</div><div class="ttdoc">LDRT Unprivileged (8 bit)</div></div>
<div class="ttc" id="astructTPI__Type_html_a4d4cd2357f72333a82a1313228287bbd"><div class="ttname"><a href="structTPI__Type.html#a4d4cd2357f72333a82a1313228287bbd">TPI_Type::TRIGGER</a></div><div class="ttdeci">__IM uint32_t TRIGGER</div><div class="ttdoc">Offset: 0xEE8 (R/ ) TRIGGER.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:289</div></div>
<div class="ttc" id="astructFPU__Type_html"><div class="ttname"><a href="structFPU__Type.html">FPU_Type</a></div><div class="ttdoc">Structure type to access the Floating Point Unit (FPU).</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:219</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga9e3ac13d8dcf4331176b624cf6234a7e"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e">__LDREXB</a></div><div class="ttdeci">uint8_t __LDREXB(volatile uint8_t *addr)</div><div class="ttdoc">LDR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="aunionIPSR__Type_html_ab46e5f1b2f4d17cfb9aca4fffcbb2fa5"><div class="ttname"><a href="unionIPSR__Type.html#ab46e5f1b2f4d17cfb9aca4fffcbb2fa5">IPSR_Type::ISR</a></div><div class="ttdeci">uint32_t ISR</div><div class="ttdoc">bit: 0.. 8 Exception number</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:32</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga263b9b2d9c06d731022873acddb6aa3f"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga263b9b2d9c06d731022873acddb6aa3f">__LDAB</a></div><div class="ttdeci">uint8_t __LDAB(volatile uint8_t *ptr)</div><div class="ttdoc">Load-Acquire (8 bit)</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_ga72f102d31af0ee4aa7a6fb7a180840f3"><div class="ttname"><a href="group__NVIC__gr.html#ga72f102d31af0ee4aa7a6fb7a180840f3">NVIC_GetEnableIRQ</a></div><div class="ttdeci">uint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Get a device specific interrupt enable status.</div></div>
<div class="ttc" id="astructTPI__Type_html"><div class="ttname"><a href="structTPI__Type.html">TPI_Type</a></div><div class="ttdoc">Structure type to access the Trace Port Interface Register (TPI).</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:276</div></div>
<div class="ttc" id="astructSCB__Type_html_ac6a860c1b8d8154a1f00d99d23b67764"><div class="ttname"><a href="structSCB__Type.html#ac6a860c1b8d8154a1f00d99d23b67764">SCB_Type::CPACR</a></div><div class="ttdeci">__IOM uint32_t CPACR</div><div class="ttdoc">Offset: 0x088 (R/W) Coprocessor Access Control Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:128</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga963cf236b73219ce78e965deb01b81a7"><div class="ttname"><a href="group__Core__Register__gr.html#ga963cf236b73219ce78e965deb01b81a7">__get_CONTROL</a></div><div class="ttdeci">uint32_t __get_CONTROL(void)</div><div class="ttdoc">Read the CONTROL register.</div></div>
<div class="ttc" id="agroup__ITM__Debug__gr_html_ga12e68e55a7badc271b948d6c7230b2a8"><div class="ttname"><a href="group__ITM__Debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a></div><div class="ttdeci">volatile int32_t ITM_RxBuffer</div><div class="ttdoc">external variable to receive characters</div><div class="ttdef"><b>Definition:</b> Ref_Debug.txt:69</div></div>
<div class="ttc" id="astructDWT__Type_html_a61c2965af5bc0643f9af65620b0e67c9"><div class="ttname"><a href="structDWT__Type.html#a61c2965af5bc0643f9af65620b0e67c9">DWT_Type::COMP0</a></div><div class="ttdeci">__IOM uint32_t COMP0</div><div class="ttdoc">Offset: 0x020 (R/W) Comparator Register 0.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:255</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_gaca76614e3091c7324aa9d60e634621bf"><div class="ttname"><a href="group__mpu8__functions.html#gaca76614e3091c7324aa9d60e634621bf">ARM_MPU_Load</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga2b5d93b8e461755b1072a03df3f1722e"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga2b5d93b8e461755b1072a03df3f1722e">__STRHT</a></div><div class="ttdeci">void __STRHT(uint16_t value, uint16_t ptr)</div><div class="ttdoc">STRT Unprivileged (16 bit)</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga335deaaa7991490e1450cb7d1e4c5197"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a></div><div class="ttdeci">uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)</div><div class="ttdoc">STR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="astructMPU__Type_html_a1658326c6762637eeef8a79bb467445e"><div class="ttname"><a href="structMPU__Type.html#a1658326c6762637eeef8a79bb467445e">MPU_Type::RASR_A1</a></div><div class="ttdeci">__IOM uint32_t RASR_A1</div><div class="ttdoc">Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:208</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_ga666eb0caeb12ec0e281415592ae89083"><div class="ttname"><a href="group__NVIC__gr.html#ga666eb0caeb12ec0e281415592ae89083">IRQn</a></div><div class="ttdeci">IRQn</div><div class="ttdoc">Definition of IRQn numbers.</div><div class="ttdef"><b>Definition:</b> Ref_NVIC.txt:384</div></div>
<div class="ttc" id="astructSysTick__Type_html_a4780a489256bb9f54d0ba8ed4de191cd"><div class="ttname"><a href="structSysTick__Type.html#a4780a489256bb9f54d0ba8ed4de191cd">SysTick_Type::LOAD</a></div><div class="ttdeci">__IOM uint32_t LOAD</div><div class="ttdoc">Offset: 0x004 (R/W) SysTick Reload Value Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:149</div></div>
<div class="ttc" id="astructTPI__Type_html_af8b7d15fa5252b733dd4b11fa1b5730a"><div class="ttname"><a href="structTPI__Type.html#af8b7d15fa5252b733dd4b11fa1b5730a">TPI_Type::CLAIMSET</a></div><div class="ttdeci">__IOM uint32_t CLAIMSET</div><div class="ttdoc">Offset: 0xFA0 (R/W) Claim tag set.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:297</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_ga6d7f220015c070c0e469948c1775ee3d"><div class="ttname"><a href="group__mpu8__functions.html#ga6d7f220015c070c0e469948c1775ee3d">ARM_MPU_SetRegion</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gadf4252e600661fd762cfc0d1a9f5b892"><div class="ttname"><a href="group__NVIC__gr.html#gadf4252e600661fd762cfc0d1a9f5b892">NVIC_GetActive</a></div><div class="ttdeci">uint32_t NVIC_GetActive(IRQn_Type IRQn)</div><div class="ttdoc">Get the device specific interrupt active status [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="agroup__coreregister__trustzone__functions_html_gaea8db21c00cfa4144ee74dc65dbd7580"><div class="ttname"><a href="group__coreregister__trustzone__functions.html#gaea8db21c00cfa4144ee74dc65dbd7580">__TZ_set_PSP_NS</a></div><div class="ttdeci">void __TZ_set_PSP_NS(uint32_t topOfProcStack)</div><div class="ttdoc">Set Process Stack Pointer (non-secure)</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga967f516afff5900cf30f1a81907cdd89"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga967f516afff5900cf30f1a81907cdd89">__USAT16</a></div><div class="ttdeci">uint32_t __USAT16(uint32_t val1, const uint32_t val2)</div><div class="ttdoc">Q setting dual 16-bit unsigned saturate.</div></div>
<div class="ttc" id="aunionxPSR__Type_html_a1a47176768f45f79076c4f5b1b534bc2"><div class="ttname"><a href="unionxPSR__Type.html#a1a47176768f45f79076c4f5b1b534bc2">xPSR_Type::w</a></div><div class="ttdeci">uint32_t w</div><div class="ttdoc">Type used for word access.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:62</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga32da759f46e52c95bcfbde5012260667"><div class="ttname"><a href="group__Core__Register__gr.html#ga32da759f46e52c95bcfbde5012260667">__get_BASEPRI</a></div><div class="ttdeci">uint32_t __get_BASEPRI(void)</div><div class="ttdoc">Read the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="astructSCB__Type_html_a0ca18ef984d132c6bf4d9b61cd00f05a"><div class="ttname"><a href="structSCB__Type.html#a0ca18ef984d132c6bf4d9b61cd00f05a">SCB_Type::ICSR</a></div><div class="ttdeci">__IOM uint32_t ICSR</div><div class="ttdoc">Offset: 0x004 (R/W) Interrupt Control and State Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:109</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga5611f7314e0c8f53da377918dfbf42ee"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga5611f7314e0c8f53da377918dfbf42ee">__SMLSLD</a></div><div class="ttdeci">uint64_t __SMLSLD(uint32_t val1, uint32_t val2, uint64_t val3)</div><div class="ttdoc">Q setting dual 16-bit signed multiply subtract with 64-bit accumulate.</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga62fa63d39cf22df348857d5f44ab64d9"><div class="ttname"><a href="group__Core__Register__gr.html#ga62fa63d39cf22df348857d5f44ab64d9">__set_BASEPRI_MAX</a></div><div class="ttdeci">void __set_BASEPRI_MAX(uint32_t basePri)</div><div class="ttdoc">Increase the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga6f26bd75ca7e3247f27b272acc10536b"><div class="ttname"><a href="group__Core__Register__gr.html#ga6f26bd75ca7e3247f27b272acc10536b">__set_FPSCR</a></div><div class="ttdeci">void __set_FPSCR(uint32_t fpscr)</div><div class="ttdoc">Set the FPSC register [only for Cortex-M4 and Cortex-M7].</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga92f5621626711931da71eaa8bf301af7"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga92f5621626711931da71eaa8bf301af7">__BKPT</a></div><div class="ttdeci">void __BKPT(uint8_t value)</div><div class="ttdoc">Set Breakpoint.</div></div>
<div class="ttc" id="agroup__coreregister__trustzone__functions_html_ga3eb150204e6d389d5b49065179b9cde5"><div class="ttname"><a href="group__coreregister__trustzone__functions.html#ga3eb150204e6d389d5b49065179b9cde5">__TZ_set_CONTROL_NS</a></div><div class="ttdeci">void __TZ_set_CONTROL_NS(uint32_t control)</div><div class="ttdoc">Set Control register (non-secure)</div></div>
<div class="ttc" id="agroup__ITM__Debug__gr_html_ga37b8f41cae703b5ff6947e271065558c"><div class="ttname"><a href="group__ITM__Debug__gr.html#ga37b8f41cae703b5ff6947e271065558c">ITM_ReceiveChar</a></div><div class="ttdeci">int32_t ITM_ReceiveChar(void)</div><div class="ttdoc">ITM Receive Character.</div></div>
<div class="ttc" id="astructITM__Type_html_a66eb82a070953f09909f39b8e516fb91"><div class="ttname"><a href="structITM__Type.html#a66eb82a070953f09909f39b8e516fb91">ITM_Type::IRR</a></div><div class="ttdeci">__IM uint32_t IRR</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:174</div></div>
<div class="ttc" id="astructITM__Type_html_a2bcec6803f28f30d5baf5e20e3517d3d"><div class="ttname"><a href="structITM__Type.html#a2bcec6803f28f30d5baf5e20e3517d3d">ITM_Type::PID7</a></div><div class="ttdeci">__IM uint32_t PID7</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:185</div></div>
<div class="ttc" id="agroup__nvic__trustzone__functions_html_ga2caf0df3603378c436c838138e42059a"><div class="ttname"><a href="group__nvic__trustzone__functions.html#ga2caf0df3603378c436c838138e42059a">TZ_NVIC_SetPriority_NS</a></div><div class="ttdeci">void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)</div><div class="ttdoc">Set Interrupt Priority (non-secure)</div></div>
<div class="ttc" id="astructNVIC__Type_html"><div class="ttname"><a href="structNVIC__Type.html">NVIC_Type</a></div><div class="ttdoc">Structure type to access the Nested Vectored Interrupt Controller (NVIC).</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:85</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_gab898559392ba027814e5bbb5a98b38d2"><div class="ttname"><a href="group__Core__Register__gr.html#gab898559392ba027814e5bbb5a98b38d2">__get_MSP</a></div><div class="ttdeci">uint32_t __get_MSP(void)</div><div class="ttdoc">Read the MSP register.</div></div>
<div class="ttc" id="astructITM__Type_html_a7f9c2a2113a11c7f3e98915f95b669d5"><div class="ttname"><a href="structITM__Type.html#a7f9c2a2113a11c7f3e98915f95b669d5">ITM_Type::LAR</a></div><div class="ttdeci">__OM uint32_t LAR</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:177</div></div>
<div class="ttc" id="astructMPU__Type_html_a769178ef949f0d5d8f18ddbd9e4e926f"><div class="ttname"><a href="structMPU__Type.html#a769178ef949f0d5d8f18ddbd9e4e926f">MPU_Type::CTRL</a></div><div class="ttdeci">__IOM uint32_t CTRL</div><div class="ttdoc">Offset: 0x004 (R/W) MPU Control Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:203</div></div>
<div class="ttc" id="astructSCnSCB__Type_html_a34ec1d771245eb9bd0e3ec9336949762"><div class="ttname"><a href="structSCnSCB__Type.html#a34ec1d771245eb9bd0e3ec9336949762">SCnSCB_Type::ICTR</a></div><div class="ttdeci">__IM uint32_t ICTR</div><div class="ttdoc">Offset: 0x004 (R/ ) Interrupt Controller Type Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:138</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gaef7e08ba1dbaaae1efdb76c113155ed1"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gaef7e08ba1dbaaae1efdb76c113155ed1">__SXTB16_RORn</a></div><div class="ttdeci">uint32_t __SXTB16_RORn(uint32_t val, uint32_r rotate)</div><div class="ttdoc">Rotate right, dual extract 8-bits and sign extend each to 16-bits.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga5290ce5564770ad124910d2583dc0a9e"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga5290ce5564770ad124910d2583dc0a9e">__SMLSDX</a></div><div class="ttdeci">uint32_t __SMLSDX(uint32_t val1, uint32_t val2, uint32_t val3)</div><div class="ttdoc">Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate.</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_gaa78e4e6bf619a65e9f01b4af13fed3a8"><div class="ttname"><a href="group__Core__Register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8">__get_FAULTMASK</a></div><div class="ttdeci">uint32_t __get_FAULTMASK(void)</div><div class="ttdoc">Read the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="astructSCB__Type_html_a2d03d0b7cec2254f39eb1c46c7445e80"><div class="ttname"><a href="structSCB__Type.html#a2d03d0b7cec2254f39eb1c46c7445e80">SCB_Type::MMFAR</a></div><div class="ttdeci">__IOM uint32_t MMFAR</div><div class="ttdoc">Offset: 0x034 (R/W) MemManage Fault Address Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:119</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_gac71fad9f0a91980fecafcb450ee0a63e"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#gac71fad9f0a91980fecafcb450ee0a63e">__NOP</a></div><div class="ttdeci">void __NOP(void)</div><div class="ttdoc">No Operation.</div></div>
<div class="ttc" id="astructSCB__Type_html_a2d6653b0b70faac936046a02809b577f"><div class="ttname"><a href="structSCB__Type.html#a2d6653b0b70faac936046a02809b577f">SCB_Type::CCR</a></div><div class="ttdeci">__IOM uint32_t CCR</div><div class="ttdoc">Offset: 0x014 (R/W) Configuration Control Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:113</div></div>
<div class="ttc" id="astructDWT__Type_html_a2c08096c82abe245c0fa97badc458154"><div class="ttname"><a href="structDWT__Type.html#a2c08096c82abe245c0fa97badc458154">DWT_Type::CPICNT</a></div><div class="ttdeci">__IOM uint32_t CPICNT</div><div class="ttdoc">Offset: 0x008 (R/W) CPI Count Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:249</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga90884c591ac5d73d6069334eba9d6c02"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga90884c591ac5d73d6069334eba9d6c02">__CLZ</a></div><div class="ttdeci">uint8_t __CLZ(uint32_t value)</div><div class="ttdoc">Count leading zeros.</div></div>
<div class="ttc" id="agroup__nvic__trustzone__functions_html_gaedea4c16dd4a0b792c7e9d1da4c49295"><div class="ttname"><a href="group__nvic__trustzone__functions.html#gaedea4c16dd4a0b792c7e9d1da4c49295">TZ_NVIC_EnableIRQ_NS</a></div><div class="ttdeci">void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)</div><div class="ttdoc">Enable External Interrupt (non-secure)</div></div>
<div class="ttc" id="aunionxPSR__Type_html_add7cbd2b0abd8954d62cd7831796ac7c"><div class="ttname"><a href="unionxPSR__Type.html#add7cbd2b0abd8954d62cd7831796ac7c">xPSR_Type::Q</a></div><div class="ttdeci">uint32_t Q</div><div class="ttdoc">bit: 27 Saturation condition flag</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:56</div></div>
<div class="ttc" id="astructDWT__Type_html_aabf94936c9340e62fed836dcfb152405"><div class="ttname"><a href="structDWT__Type.html#aabf94936c9340e62fed836dcfb152405">DWT_Type::MASK1</a></div><div class="ttdeci">__IOM uint32_t MASK1</div><div class="ttdoc">Offset: 0x034 (R/W) Mask Register 1.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:260</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gaebee9cad6724a5bac1857f0f1fb6d6af"><div class="ttname"><a href="group__NVIC__gr.html#gaebee9cad6724a5bac1857f0f1fb6d6af">NVIC_GetVector</a></div><div class="ttdeci">uint32_t NVIC_GetVector(IRQn_Type IRQn)</div><div class="ttdoc">Read Interrupt Vector [not for Cortex-M0, SC000].</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_gaf66beb577bb9d90424c3d1d7f684c024"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#gaf66beb577bb9d90424c3d1d7f684c024">__ROR</a></div><div class="ttdeci">uint32_t __ROR(uint32_t value, uint32_t shift)</div><div class="ttdoc">Rotate a value right by a number of bits.</div></div>
<div class="ttc" id="astructDWT__Type_html_a38714af6b7fa7c64d68f5e1efbe7a931"><div class="ttname"><a href="structDWT__Type.html#a38714af6b7fa7c64d68f5e1efbe7a931">DWT_Type::COMP1</a></div><div class="ttdeci">__IOM uint32_t COMP1</div><div class="ttdoc">Offset: 0x030 (R/W) Comparator Register 1.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:259</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gad089605c16df9823a2c8aaa37777aae5"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gad089605c16df9823a2c8aaa37777aae5">__QSUB16</a></div><div class="ttdeci">uint32_t __QSUB16(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Q setting dual 16-bit saturating subtract.</div></div>
<div class="ttc" id="astructITM__Type_html_af9085648bf18f69b5f9d1136d45e1d37"><div class="ttname"><a href="structITM__Type.html#af9085648bf18f69b5f9d1136d45e1d37">ITM_Type::PID5</a></div><div class="ttdeci">__IM uint32_t PID5</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:183</div></div>
<div class="ttc" id="astructSCnSCB__Type_html"><div class="ttname"><a href="structSCnSCB__Type.html">SCnSCB_Type</a></div><div class="ttdoc">Structure type to access the System Control and ID Register not in the SCB.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:135</div></div>
<div class="ttc" id="astructSysTick__Type_html_a875e7afa5c4fd43997fb544a4ac6e37e"><div class="ttname"><a href="structSysTick__Type.html#a875e7afa5c4fd43997fb544a4ac6e37e">SysTick_Type::CTRL</a></div><div class="ttdeci">__IOM uint32_t CTRL</div><div class="ttdoc">Offset: 0x000 (R/W) SysTick Control and Status Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:148</div></div>
<div class="ttc" id="astructARM__MPU__Region__t_html_ab5d3a650dbffd0b272bf7df5b140e8a8"><div class="ttname"><a href="structARM__MPU__Region__t.html#ab5d3a650dbffd0b272bf7df5b140e8a8">ARM_MPU_Region_t::RLAR</a></div><div class="ttdeci">uint32_t RLAR</div><div class="ttdef"><b>Definition:</b> Ref_MPU8.txt:106</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga17b873f246c9f5e9355760ffef3dad4a"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga17b873f246c9f5e9355760ffef3dad4a">__QADD</a></div><div class="ttdeci">uint32_t __QADD(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Q setting saturating add.</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_ga389f9b6049d176bc83f9964d3259b712"><div class="ttname"><a href="group__mpu8__functions.html#ga389f9b6049d176bc83f9964d3259b712">ARM_MPU_Disable_NS</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_Disable_NS(void)</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga6809a07c5cb7410e361f3fba57f72172"><div class="ttname"><a href="group__Core__Register__gr.html#ga6809a07c5cb7410e361f3fba57f72172">__set_MSPLIM</a></div><div class="ttdeci">__set_MSPLIM(uint32_t MainStackPtrLimit)</div><div class="ttdoc">Set Main Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-s...</div></div>
<div class="ttc" id="astructTPI__Type_html_abc0ecda8a5446bc754080276bad77514"><div class="ttname"><a href="structTPI__Type.html#abc0ecda8a5446bc754080276bad77514">TPI_Type::DEVID</a></div><div class="ttdeci">__IM uint32_t DEVID</div><div class="ttdoc">Offset: 0xFC8 (R/ ) TPIU_DEVID.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:300</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga8cfeb5ffe0e49ec6b29dafdde92e5118"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga8cfeb5ffe0e49ec6b29dafdde92e5118">__SSAT</a></div><div class="ttdeci">int32_t __SSAT(int32_t value, uint32_t sat)</div><div class="ttdoc">Signed Saturate [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="agroup__nvic__trustzone__functions_html_ga57d2a6736704c4a39421ed1a2e7b689b"><div class="ttname"><a href="group__nvic__trustzone__functions.html#ga57d2a6736704c4a39421ed1a2e7b689b">TZ_NVIC_GetEnableIRQ_NS</a></div><div class="ttdeci">uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)</div><div class="ttdoc">Get Interrupt Enable status (non-secure)</div></div>
<div class="ttc" id="agroup__nvic__trustzone__functions_html_ga3b30f8b602b593a806617b671a50731a"><div class="ttname"><a href="group__nvic__trustzone__functions.html#ga3b30f8b602b593a806617b671a50731a">TZ_NVIC_ClearPendingIRQ_NS</a></div><div class="ttdeci">void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)</div><div class="ttdoc">Clear Pending Interrupt (non-secure)</div></div>
<div class="ttc" id="aunionxPSR__Type_html_a3200966922a194d84425e2807a7f1328"><div class="ttname"><a href="unionxPSR__Type.html#a3200966922a194d84425e2807a7f1328">xPSR_Type::IT</a></div><div class="ttdeci">uint32_t IT</div><div class="ttdoc">bit: 25..26 saved IT state (read 0)</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:55</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_gac1a949403bf84eecaf407003fb553ae7"><div class="ttname"><a href="group__mpu8__functions.html#gac1a949403bf84eecaf407003fb553ae7">ARM_MPU_OrderedMemcpy</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga48e5853f417e17a8a65080f6a605b743"><div class="ttname"><a href="group__Core__Register__gr.html#ga48e5853f417e17a8a65080f6a605b743">__set_PSP</a></div><div class="ttdeci">void __set_PSP(uint32_t topOfProcStack)</div><div class="ttdoc">Set the PSP register.</div></div>
<div class="ttc" id="astructITM__Type_html_a2372a4ebb63e36d1eb3fcf83a74fd537"><div class="ttname"><a href="structITM__Type.html#a2372a4ebb63e36d1eb3fcf83a74fd537">ITM_Type::DEVARCH</a></div><div class="ttdeci">__IM uint32_t DEVARCH</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:180</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga590724a32a229978536fbbbd6cc82536"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga590724a32a229978536fbbbd6cc82536">__STLEXB</a></div><div class="ttdeci">uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)</div><div class="ttdoc">Store-Release Exclusive (8 bit)</div></div>
<div class="ttc" id="agroup__mpu__functions_html_ga16931f9ad84d7289e8218e169ae6db5d"><div class="ttname"><a href="group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d">ARM_MPU_SetRegion</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gac540b4fc41d30778ba102d2a65db5589"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gac540b4fc41d30778ba102d2a65db5589">__SXTAB16</a></div><div class="ttdeci">uint32_t __SXTAB16(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Dual extracted 8-bit to 16-bit signed addition.</div></div>
<div class="ttc" id="astructSysTick__Type_html_afcadb0c6d35b21cdc0018658a13942de"><div class="ttname"><a href="structSysTick__Type.html#afcadb0c6d35b21cdc0018658a13942de">SysTick_Type::CALIB</a></div><div class="ttdeci">__IM uint32_t CALIB</div><div class="ttdoc">Offset: 0x00C (R/ ) SysTick Calibration Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:151</div></div>
<div class="ttc" id="astructCoreDebug__Type_html_aab3cc92ef07bc1f04b3a3aa6db2c2d55"><div class="ttname"><a href="structCoreDebug__Type.html#aab3cc92ef07bc1f04b3a3aa6db2c2d55">CoreDebug_Type::DCRDR</a></div><div class="ttdeci">__IOM uint32_t DCRDR</div><div class="ttdoc">Offset: 0x008 (R/W) Debug Core Register Data Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:237</div></div>
<div class="ttc" id="agroup__compiler__conntrol__gr_html_ga84b0bad4aa39632d3faea46aa1e102a8"><div class="ttname"><a href="group__compiler__conntrol__gr.html#ga84b0bad4aa39632d3faea46aa1e102a8">__STACK_LIMIT</a></div><div class="ttdeci">#define __STACK_LIMIT</div><div class="ttdoc">Compiler/linker symbol specifiying the limit of the main stack (MSP).</div><div class="ttdef"><b>Definition:</b> Ref_CompilerControl.txt:482</div></div>
<div class="ttc" id="agroup__system__init__gr_html_gaa3cd3e43291e81e795d642b79b6088e6"><div class="ttname"><a href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a></div><div class="ttdeci">uint32_t SystemCoreClock</div><div class="ttdoc">Variable to hold the system core clock value.</div><div class="ttdef"><b>Definition:</b> Ref_SystemAndClock.txt:68</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_gad41aa59c92c0a165b7f98428d3320cd5"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#gad41aa59c92c0a165b7f98428d3320cd5">__STRBT</a></div><div class="ttdeci">void __STRBT(uint8_t value, uint8_t ptr)</div><div class="ttdoc">STRT Unprivileged (8 bit)</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_gaea60757232f740ec6b09980eebb614ff"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#gaea60757232f740ec6b09980eebb614ff">__SMMLA</a></div><div class="ttdeci">uint32_t __SMMLA(int32_t val1, int32_t val2, int32_t val3)</div><div class="ttdoc">32-bit signed multiply with 32-bit truncated accumulator.</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga9d3bc5c539f9bd50f7d59ffa37ac6a65"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga9d3bc5c539f9bd50f7d59ffa37ac6a65">__SSAX</a></div><div class="ttdeci">uint32_t __SSAX(uint32_t val1, uint32_t val2)</div><div class="ttdoc">GE setting dual 16-bit signed subtraction and addition with exchange.</div></div>
<div class="ttc" id="agroup__coreregister__trustzone__functions_html_gab7263167cb006aeeb04b68e579dae015"><div class="ttname"><a href="group__coreregister__trustzone__functions.html#gab7263167cb006aeeb04b68e579dae015">__TZ_set_SP_NS</a></div><div class="ttdeci">void __TZ_set_SP_NS(uint32_t topOfStack)</div><div class="ttdoc">Set Stack Pointer (non-secure)</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga3c34da7eb16496ae2668a5b95fa441e7"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga3c34da7eb16496ae2668a5b95fa441e7">__SEV</a></div><div class="ttdeci">void __SEV(void)</div><div class="ttdoc">Send Event.</div></div>
<div class="ttc" id="astructTPI__Type_html_a8826aa84e5806053395a742d38d59d0f"><div class="ttname"><a href="structTPI__Type.html#a8826aa84e5806053395a742d38d59d0f">TPI_Type::CSPSR</a></div><div class="ttdeci">__IOM uint32_t CSPSR</div><div class="ttdoc">Offset: 0x004 (R/W) Current Parallel Port Size Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:279</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga360c73eb7ffb16088556f9278953b882"><div class="ttname"><a href="group__Core__Register__gr.html#ga360c73eb7ffb16088556f9278953b882">__set_BASEPRI</a></div><div class="ttdeci">void __set_BASEPRI(uint32_t basePri)</div><div class="ttdoc">Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_gaeb8e5f7564a8ea23678fe3c987b04013"><div class="ttname"><a href="group__Core__Register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">__disable_irq</a></div><div class="ttdeci">void __disable_irq(void)</div><div class="ttdoc">Globally disables interrupts and configurable fault handlers.</div></div>
<div class="ttc" id="aunionAPSR__Type_html_a22d10913489d24ab08bd83457daa88de"><div class="ttname"><a href="unionAPSR__Type.html#a22d10913489d24ab08bd83457daa88de">APSR_Type::Q</a></div><div class="ttdeci">uint32_t Q</div><div class="ttdoc">bit: 27 Saturation condition flag</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:15</div></div>
<div class="ttc" id="agroup__nvic__trustzone__functions_html_gaf5f578628bc8b7154b29577f6f6a87fd"><div class="ttname"><a href="group__nvic__trustzone__functions.html#gaf5f578628bc8b7154b29577f6f6a87fd">TZ_NVIC_GetPriorityGrouping_NS</a></div><div class="ttdeci">uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)</div><div class="ttdoc">Get Priority Grouping (non-secure)</div></div>
<div class="ttc" id="astructDWT__Type_html_a8dfcf25675f9606aa305c46e85182e4e"><div class="ttname"><a href="structDWT__Type.html#a8dfcf25675f9606aa305c46e85182e4e">DWT_Type::FUNCTION1</a></div><div class="ttdeci">__IOM uint32_t FUNCTION1</div><div class="ttdoc">Offset: 0x038 (R/W) Function Register 1.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:261</div></div>
<div class="ttc" id="astructMPU__Type_html_a7d15172b163797736a6c6b4dcc0fa3dd"><div class="ttname"><a href="structMPU__Type.html#a7d15172b163797736a6c6b4dcc0fa3dd">MPU_Type::RASR_A3</a></div><div class="ttdeci">__IOM uint32_t RASR_A3</div><div class="ttdoc">Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:212</div></div>
<div class="ttc" id="astructTPI__Type_html_aaa573b2e073e76e93c51ecec79c616d0"><div class="ttname"><a href="structTPI__Type.html#aaa573b2e073e76e93c51ecec79c616d0">TPI_Type::ITATBCTR0</a></div><div class="ttdeci">__IM uint32_t ITATBCTR0</div><div class="ttdoc">Offset: 0xEF8 (R/ ) ITATBCTR0.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:293</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_gga666eb0caeb12ec0e281415592ae89083a8693500eff174f16119e96234fee73af"><div class="ttname"><a href="group__NVIC__gr.html#gga666eb0caeb12ec0e281415592ae89083a8693500eff174f16119e96234fee73af">BusFault_IRQn</a></div><div class="ttdeci">@ BusFault_IRQn</div><div class="ttdoc">Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants].</div><div class="ttdef"><b>Definition:</b> Ref_NVIC.txt:390</div></div>
<div class="ttc" id="aunionxPSR__Type_html_a1e5d9801013d5146f2e02d9b7b3da562"><div class="ttname"><a href="unionxPSR__Type.html#a1e5d9801013d5146f2e02d9b7b3da562">xPSR_Type::Z</a></div><div class="ttdeci">uint32_t Z</div><div class="ttdoc">bit: 30 Zero condition code flag</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:59</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_ga5810ac0b87a37e321c2f909cd3860499"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#ga5810ac0b87a37e321c2f909cd3860499">__LDAH</a></div><div class="ttdeci">uint16_t __LDAH(volatile uint16_t *ptr)</div><div class="ttdoc">Load-Acquire (16 bit)</div></div>
<div class="ttc" id="aRef__Peripheral_8txt_html_a139b6e261c981f014f386927ca4a8444"><div class="ttname"><a href="Ref__Peripheral_8txt.html#a139b6e261c981f014f386927ca4a8444">_FLD2VAL</a></div><div class="ttdeci">#define _FLD2VAL(field, value)</div><div class="ttdoc">Extract from a peripheral register value the a bit field value.</div><div class="ttdef"><b>Definition:</b> Ref_Peripheral.txt:226</div></div>
<div class="ttc" id="astructSysTick__Type_html"><div class="ttname"><a href="structSysTick__Type.html">SysTick_Type</a></div><div class="ttdoc">Structure type to access the System Timer (SysTick).</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:146</div></div>
<div class="ttc" id="astructTPI__Type_html_a7b72598e20066133e505bb781690dc22"><div class="ttname"><a href="structTPI__Type.html#a7b72598e20066133e505bb781690dc22">TPI_Type::SSPSR</a></div><div class="ttdeci">__IOM uint32_t SSPSR</div><div class="ttdoc">Offset: 0x000 (R/ ) Supported Parallel Port Size Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:278</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_ga6575d37863cec5d334864f93b5b783bf"><div class="ttname"><a href="group__Core__Register__gr.html#ga6575d37863cec5d334864f93b5b783bf">__enable_fault_irq</a></div><div class="ttdeci">void __enable_fault_irq(void)</div><div class="ttdoc">Enables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000].</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_ga3d50ba8546252bea959e45c8fdf16993"><div class="ttname"><a href="group__mpu8__functions.html#ga3d50ba8546252bea959e45c8fdf16993">ARM_MPU_SetRegionEx</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type *mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)</div></div>
<div class="ttc" id="agroup__intrinsic__CPU__gr_html_gad6f9f297f6b91a995ee199fbc796b863"><div class="ttname"><a href="group__intrinsic__CPU__gr.html#gad6f9f297f6b91a995ee199fbc796b863">__RBIT</a></div><div class="ttdeci">uint32_t __RBIT(uint32_t value)</div><div class="ttdoc">Reverse bit order of value.</div></div>
<div class="ttc" id="aunionIPSR__Type_html"><div class="ttname"><a href="unionIPSR__Type.html">IPSR_Type</a></div><div class="ttdoc">Union type to access the Interrupt Program Status Register (IPSR).</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:28</div></div>
<div class="ttc" id="agroup__Core__Register__gr_html_gaf39856ca50fc88cf459031b44eb2521c"><div class="ttname"><a href="group__Core__Register__gr.html#gaf39856ca50fc88cf459031b44eb2521c">__get_MSPLIM</a></div><div class="ttdeci">uint32_t __get_MSPLIM(void)</div><div class="ttdoc">Get Main Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-s...</div></div>
<div class="ttc" id="agroup__compiler__conntrol__gr_html_ga72db8b026c5e100254080fefabd9fd88"><div class="ttname"><a href="group__compiler__conntrol__gr.html#ga72db8b026c5e100254080fefabd9fd88">__PROGRAM_START</a></div><div class="ttdeci">#define __PROGRAM_START</div><div class="ttdoc">Entry function into the user application or library startup.</div><div class="ttdef"><b>Definition:</b> Ref_CompilerControl.txt:447</div></div>
<div class="ttc" id="agroup__coreregister__trustzone__functions_html_gab3aa15eb4f352e230b9f7a3e8856a9e9"><div class="ttname"><a href="group__coreregister__trustzone__functions.html#gab3aa15eb4f352e230b9f7a3e8856a9e9">__TZ_get_MSP_NS</a></div><div class="ttdeci">uint32_t __TZ_get_MSP_NS(void)</div><div class="ttdoc">Get Main Stack Pointer (non-secure)</div></div>
<div class="ttc" id="astructITM__Type_html_a5834885903a557674f078f3b71fa8bc8"><div class="ttname"><a href="structITM__Type.html#a5834885903a557674f078f3b71fa8bc8">ITM_Type::u32</a></div><div class="ttdeci">__OM uint32_t u32</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:164</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga9f2b77e11fc4a77b26c36c423ed45b4e"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga9f2b77e11fc4a77b26c36c423ed45b4e">__USUB16</a></div><div class="ttdeci">uint32_t __USUB16(uint32_t val1, uint32_t val2)</div><div class="ttdoc">GE setting dual 16-bit unsigned subtract.</div></div>
<div class="ttc" id="astructITM__Type_html_a04b9fbc83759cb818dfa161d39628426"><div class="ttname"><a href="structITM__Type.html#a04b9fbc83759cb818dfa161d39628426">ITM_Type::TCR</a></div><div class="ttdeci">__IOM uint32_t TCR</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:171</div></div>
<div class="ttc" id="agroup__SysTick__gr_html_gabe47de40e9b0ad465b752297a9d9f427"><div class="ttname"><a href="group__SysTick__gr.html#gabe47de40e9b0ad465b752297a9d9f427">SysTick_Config</a></div><div class="ttdeci">uint32_t SysTick_Config(uint32_t ticks)</div><div class="ttdoc">System Tick Timer Configuration.</div></div>
<div class="ttc" id="agroup__mpu8__functions_html_ga7566931ca9bb9f22d213a67ec5f8c745"><div class="ttname"><a href="group__mpu8__functions.html#ga7566931ca9bb9f22d213a67ec5f8c745">ARM_MPU_SetRegion_NS</a></div><div class="ttdeci">__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)</div></div>
<div class="ttc" id="astructCoreDebug__Type_html_ad63554e4650da91a8e79929cbb63db66"><div class="ttname"><a href="structCoreDebug__Type.html#ad63554e4650da91a8e79929cbb63db66">CoreDebug_Type::DHCSR</a></div><div class="ttdeci">__IOM uint32_t DHCSR</div><div class="ttdoc">Offset: 0x000 (R/W) Debug Halting Control and Status Register.</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:235</div></div>
<div class="ttc" id="agroup__coreregister__trustzone__functions_html_ga7cc3271c79e619f8838e8767df3cb509"><div class="ttname"><a href="group__coreregister__trustzone__functions.html#ga7cc3271c79e619f8838e8767df3cb509">__TZ_get_PRIMASK_NS</a></div><div class="ttdeci">uint32_t __TZ_get_PRIMASK_NS(void)</div><div class="ttdoc">Get Priority Mask (non-secure)</div></div>
<div class="ttc" id="agroup__intrinsic__SIMD__gr_html_ga15d8899a173effb8ad8c7268da32b60e"><div class="ttname"><a href="group__intrinsic__SIMD__gr.html#ga15d8899a173effb8ad8c7268da32b60e">__SHADD16</a></div><div class="ttdeci">uint32_t __SHADD16(uint32_t val1, uint32_t val2)</div><div class="ttdoc">Dual 16-bit signed addition with halved results.</div></div>
<div class="ttc" id="agroup__sau__trustzone__functions_html_ga187377409289e34838225ce801fb102c"><div class="ttname"><a href="group__sau__trustzone__functions.html#ga187377409289e34838225ce801fb102c">TZ_SAU_Enable</a></div><div class="ttdeci">void TZ_SAU_Enable(void)</div><div class="ttdoc">Enable Security Attribution Unit (SAU)</div></div>
<div class="ttc" id="agroup__NVIC__gr_html_ga382ad6bedd6eecfdabd1b94dd128a01a"><div class="ttname"><a href="group__NVIC__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a">NVIC_ClearPendingIRQ</a></div><div class="ttdeci">void NVIC_ClearPendingIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Clear a device specific interrupt from pending</div></div>
<div class="ttc" id="aunionCONTROL__Type_html_a35c1732cf153b7b5c4bd321cf1de9605"><div class="ttname"><a href="unionCONTROL__Type.html#a35c1732cf153b7b5c4bd321cf1de9605">CONTROL_Type::nPRIV</a></div><div class="ttdeci">uint32_t nPRIV</div><div class="ttdoc">bit: 0 Execution privilege in Thread mode</div><div class="ttdef"><b>Definition:</b> Ref_DataStructs.txt:73</div></div>
<div class="ttc" id="agroup__Dcache__functions__m7_html_ga503ef7ef58c0773defd15a82f6336c09"><div class="ttname"><a href="group__Dcache__functions__m7.html#ga503ef7ef58c0773defd15a82f6336c09">SCB_InvalidateDCache_by_Addr</a></div><div class="ttdeci">__STATIC_INLINE void SCB_InvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize)</div><div class="ttdoc">D-Cache Invalidate by address.</div></div>
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